Efficient design of multi-rate low-density parity-check code decoder
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摘要: 设计了一种高效的多码率LDPC(Low Density Parity Check)码译码器结构,提出了一种校验节点更新单元(CNU,Check Node Updating Units)与变量节点更新单元(VNU,Variable Node Updating Units)的设计方法.按照"化整为零"的思想,将CNU与VNU分成若干小的运算单元,在不同码率下对这些运算单元进行动态组合构成新的CNU与VNU,从而减少不同码率下硬件资源的冗余,提高了译码速率.最后,按照本文提出的译码器结构,使用Altera公司Stratix系列的FPGA EP1S80实现了中国数字电视地面广播传输标准中使用的0.4,0.6和0.8三种码率LDPC码的译码器.实现结果表明:该结构的多码率译码器仅比单码率译码器多耗用12％的硬件逻辑资源,存储器相当;而相对于传统的多码率译码器结构,本结构在不增加硬件资源的情况下,将0.4码率码字的译码速率提高了100％,将0.6码率码字的译码速率提高了50％.
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关键词:
- 低密度奇偶校验码 /
- 置信概率传播译码方法 /
- 多码率
Abstract: An efficient partially parallel decoder architecture suited for multi-rate low density parity check(LDPC) codes was presented. Algorithmic transformation and architectural level optimization were incorporated to reduce the critical path. The check node updating units (CNU) and the variable node updating units (VNU) were divided several smaller parts, which are dynamically grouped under different code rate according to the row the column weights of check matrix. This method brings in great redundancy reduction of CNU and VNU, and the decoding rate was increased significantly for the small row-weight (column-weight) codes. Based on the proposed architectures, a 7k-lenth multi-rate LDPC code of rate 0.4, 0.6 and 0.8 decoder was described using verilog hardware design language and implemented on Altera field programmable gate array (FPGA) Stratix EP1S80. The implementation results show that this multi-rate decoder is just 12% larger in logic core size than a single rate decoder. Compared with the conventional partially parallel decoder, this decoder increases the throughput of rate 0.4 code is increased by 100% and rate 0.6 code by 50% without any hardware resource incensement and performance loss. -
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