留言板

尊敬的读者、作者、审稿人, 关于本刊的投稿、审稿、编辑和出版的任何问题, 您可以本页添加留言。我们将尽快给您答复。谢谢您的支持!

姓名
邮箱
手机号码
标题
留言内容
验证码

热效应布局下的缓冲器插入时序优化方法

王新胜 韩良 喻明艳

王新胜, 韩良, 喻明艳等 . 热效应布局下的缓冲器插入时序优化方法[J]. 北京航空航天大学学报, 2015, 41(10): 1813-1820. doi: 10.13700/j.bh.1001-5965.2014.0809
引用本文: 王新胜, 韩良, 喻明艳等 . 热效应布局下的缓冲器插入时序优化方法[J]. 北京航空航天大学学报, 2015, 41(10): 1813-1820. doi: 10.13700/j.bh.1001-5965.2014.0809
WANG Xinsheng, HAN Liang, YU Mingyanet al. Thermal aware floor planning timing optimal method for buffer insertion[J]. Journal of Beijing University of Aeronautics and Astronautics, 2015, 41(10): 1813-1820. doi: 10.13700/j.bh.1001-5965.2014.0809(in Chinese)
Citation: WANG Xinsheng, HAN Liang, YU Mingyanet al. Thermal aware floor planning timing optimal method for buffer insertion[J]. Journal of Beijing University of Aeronautics and Astronautics, 2015, 41(10): 1813-1820. doi: 10.13700/j.bh.1001-5965.2014.0809(in Chinese)

热效应布局下的缓冲器插入时序优化方法

doi: 10.13700/j.bh.1001-5965.2014.0809
基金项目: 国家自然科学基金(61201307)
详细信息
    作者简介:

    王新胜(1978-),男,山东威海人,讲师,xswang@hit.edu.cn

    通讯作者:

    韩良(1969-),男,吉林榆树人,副教授,hanliang@hit.edu.cn,主要研究方向为大规模集成电路设计.

  • 中图分类号: TN405.97;TN402

Thermal aware floor planning timing optimal method for buffer insertion

  • 摘要: 随着集成电路的集成度越来越高,芯片的发热量越来越大且其内部温度呈不均匀分布,这会影响关键路径的传播延时,进而影响基于缓冲器插入的关键路径性能.提出了一种考虑芯片热效应布局优化的缓冲器插入时序优化方法,在版图设计的早期估计芯片的热分布和温度分布并且把其应用到版图布局优化和RC延时模型中.同时利用模拟退火算法基于热分布调整并优化布局,最后在最优布局下利用提出的缓冲器插入模型和快速插入算法进行时序优化.仿真结果表明相对于不考虑温度效应布局优化的缓冲器插入方法,缓冲器插入延时优化方法能有效降低最坏延时和缓冲器插入数目,最坏延时比传统方法降低9%~18%,比文献已经提出的最好方法降低5%~7%,缓冲器插入数比其少10~20个.

     

  • [1] Tsai C H,Kang S M.Cell-level placement for improving substrate thermal distribution[J].IEEE Transactions on Computer-Aided Design for Integrated Circuits and Systems,2000,19(2):253-266.
    [2] Ajami A H,Banerjee K,Pedram M.Modeling and analysis of non-uniform substrate temperature effects on global ULSI interconnects[J].IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems,2005,24(6):849-861.
    [3] Ajami A H,Banerjee K,Pedram M.Analysis of substrate thermal gradient effects on optimal buffer insertion[C]∥IEEE ACM International Conference on ICCAD.Piscataway,NJ:IEEE Press,2001:44-48.
    [4] Huang W,Ghosh S,Velusamy S,et al.HotSpot:A compact thermal modeling methodology for early-stage VLSI design[J].IEEE Transactions on Very Large Scale Integration Systems,2006,14(5):501-513.
    [5] Sankaranarayanan K,Velusamy S,Stan M R,et al.A case for thermal-aware floorplanning at the microarchitectural level[J].Journal of Instruction-Level Parallelism,2005(8):1-16.
    [6] Saxena P,Menezes N,Cocchini P,et al.Repeater scaling and its impact on CAD[J].IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems,2004,23(4):451-463.
    [7] Kim M,Ahn B G,Kim J,et al.Thermal aware timing budget for buffer insertion in early stage of physical design[C]∥IEEE International Symposium on Circuit and Systems.Piscataway,NJ:IEEE Press,2012:357-360.
    [8] Kirkpatrick S.Optimization by simulated annealing:Quantitative studies[J].Journal of Statistical Physics,1983,34(5-6):975-986.
    [9] Kevin S.HotSpot[EB/OL].2014[2015-03-22].http:∥lava.cs.virginia.edu/hotspot.
    [10] Kevin S.HotSpot[EB/OL].2014[2015-03-22].http:∥lava.cs.virginia.edu/HotSpot/HotSpotHowTo.htm.
    [11] van Ginneken L P P P.Buffer placement in distributed RC-tree networks for minmal elmore delay[C]∥IEEE International Symposium on Circuits and Systems.Piscataway,NJ:IEEE Press,1990:865-868.
    [12] Gupta R,Tutuianu B,Pileggi L T.The Elmore delay as a bound for RC trees with generalized input signals[J].IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems,1997,16(1):95-104.
    [13] Abou A I,Nowak B,Chu C.Fitted Elmore delay:A simple and accurate interconnect delay model[J].IEEE Transactions on Very Large Scale Integration System.Piscataway,NJ:IEEE Press,2004,12(7):691-696.
    [14] Athikulwongse K,Zhao X,Lim S K.Buffered clock tree sizing for skew minimization under power and thermal budgets[C]∥Proceedings of the 2010 Asia and South Pacific Design Automation Conference.Piscataway,NJ:IEEE Press,2010:474-479.
    [15] Skadron K,Stan M,Velusamy S,et al.A case for thermal aware floor planning at the microarchitectural level[J].Journal of Instruction-level Parallelism,2005,7:1-16.
    [16] Patrick H M,Ameya R A.GSRC bookshelf benchmarks[EB/OL].2001(2007-06-01)[2015-03-22].http:∥vlsicad.cs.binghamton.edu/benchgsrc.html.
    [17] Yu C.Predictive technology model[EB/OL].Arizona:[s.n.],2005(2012-06-01)[2015-03-22].http:∥ptm.asu.edu/.
  • 加载中
计量
  • 文章访问数:  737
  • HTML全文浏览量:  117
  • PDF下载量:  474
  • 被引次数: 0
出版历程
  • 收稿日期:  2014-12-23
  • 修回日期:  2015-02-12
  • 网络出版日期:  2015-10-20

目录

    /

    返回文章
    返回
    常见问答