北京航空航天大学学报 ›› 2019, Vol. 45 ›› Issue (4): 821-826.doi: 10.13700/j.bh.1001-5965.2018.0464

• 论文 • 上一篇    下一篇

一种混合粒度奇偶校验故障注入检测方法

王沛晶1,2, 刘强1,2   

  1. 1. 天津大学 微电子学院, 天津 300072;
    2. 天津市成像与感知微电子技术重点实验室, 天津 300072
  • 收稿日期:2018-08-03 出版日期:2019-04-20 发布日期:2019-04-26
  • 通讯作者: 刘强 E-mail:qiangliu@tju.edu.cn
  • 作者简介:王沛晶,女,硕士研究生。主要研究方向:集成电路安全;刘强,男,博士,副教授,博士生导师。主要研究方向:大规模集成电路设计与安全。
  • 基金资助:
    国家自然科学基金(61574099)

Mixed-grain parity-code-based fault detection method against fault injection

WANG Peijing1,2, LIU Qiang1,2   

  1. 1. School of Microelectronics, Tianjin University, Tianjin 300072, China;
    2. Tianjin Key Laboratory of Imaging and Sensing Microelectronic Technology, Tianjin 300072, China
  • Received:2018-08-03 Online:2019-04-20 Published:2019-04-26
  • Supported by:
    National Natural Science Foundation of China (61574099)

摘要: 为了实现高效的抗故障注入攻击,提出了一种混合粒度奇偶校验故障注入检测方法。传统奇偶校验检测方法为每n比特设置一个奇偶位,表示该n比特的奇偶性。随着n的减小,奇偶位个数增加,资源消耗增加,检测率提高。为了实现故障检测率和资源消耗的折中,对电路故障注入敏感部分或关键部分处理的数据采用细粒度奇偶校验(即n值较小),对其他部分采用粗粒度奇偶校验。以RC5加密算法为例,阐述了混合粒度奇偶校验故障检测方法的原理和应用,并对不同粒度奇偶校验方法的故障检测率及资源使用进行了理论分析。实验结果表明,与整个RC5电路都采用字(n=32 bit)奇偶校验相比,混合粒度奇偶校验故障注入检测方法可以提高故障检测率29.44%,仅增加资源消耗2.48%。

关键词: 奇偶校验, 混合粒度故障检测, 故障检测率, 故障注入攻击, 现场可编程门阵列(FPGA)

Abstract: For efficient countermeasure against fault injection attacks, a mixed-grain parity-code-based fault detection approach was proposed. Traditional parity-code-based fault detection approach assigns a parity bit per n bits, representing the parity of the n-bit word. As n decreases, the number of parity bits increases, leading to increased resource usage and fault detection rate. To achieve tradeoff between fault coverage and resource usage, the fine-grain parity code (small n) was applied to the data processed in the fault-sensitive parts or critical parts of circuits, and the coarse-grain parity code was applied to other parts of circuits. The approach was applied to RC5 encryption algorithm to explain the principle and application of the mixed-grain parity-code-based fault detection technology, and to theoretically analyze the fault coverage and resource usage of different grain solutions. The experimental results show that, compared to the RC5 circuit with one parity bit per 32 bit, the mixed-grain parity-code-based detection approach improves the fault coverage by 29.44% and increases resource usage slightly by 2.48%.

Key words: parity code, mixed-grain fault detection, fault coverage, fault injection attack, field programmable gate array (FPGA)

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