北京航空航天大学学报 ›› 2020, Vol. 46 ›› Issue (8): 1601-1609.doi: 10.13700/j.bh.1001-5965.2019.0530

• 论文 • 上一篇    下一篇

基于EDT的扫描测试压缩电路优化方法

李松1,2, 赵毅强1,2, 叶茂1,2   

  1. 1. 天津大学 微电子学院, 天津 300072;
    2. 天津市成像与感知微电子技术重点实验室, 天津 300072
  • 收稿日期:2019-09-29 发布日期:2020-08-27
  • 通讯作者: 李松 E-mail:keepls_833@163.com
  • 作者简介:李松 男,硕士研究生。主要研究方向:集成电路可测试性设计。
    赵毅强 男,博士,教授,博士生导师。主要研究方向:射频集成电路设计、混合信号集成电路设计、集成电路安全检测技术、安全存储芯片设计、抗攻击技术、光电检测与成像系统设计、传感器系统设计。
    叶茂 男,博士,副教授,硕士生导师。主要研究方向:混合信号集成电路设计。

Optimization method of scan test compression circuit based on EDT

LI Song1,2, ZHAO Yiqiang1,2, YE Mao1,2   

  1. 1. School of Microelectronics, Tianjin University, Tianjin 300072, China;
    2. Tianjin Key Laboratory of Imaging and Sensing Microelectronic Technology, Tianjin 300072, China
  • Received:2019-09-29 Published:2020-08-27

摘要: 为了在集成电路可测试性设计(DFT)中实现更有效的测试向量压缩,减少测试数据容量和测试时间,采用嵌入式确定性测试(EDT)的扫描测试压缩方案分别对S13207、S15850、S38417和S38584基准电路进行了优化分析,通过研究测试向量和移位周期等影响测试压缩的因素,提出了固定测试端口和固定压缩率的扫描测试压缩电路优化方法。结果表明,在测试端口数量都为2,压缩率分别为12、14、16和24时具有较好的压缩效果,与传统自动测试向量生成(ATPG)相比,固定故障的测试数据容量减小了3.9~6.4倍,测试时间减少了3.8~6.2倍,跳变延时故障的测试数据容量减少了4.1~5.4倍,测试时间减少了3.8~5.2倍。所提方法通过改变测试端口数和压缩率的方式讨论了多种影响测试压缩的因素,给出扫描测试压缩电路的优化设计方案,提高了压缩效率,并对一个较大规模电路进行了仿真验证,可适用于集成电路的扫描测试压缩设计。

关键词: 可测试性设计(DFT), 扫描测试压缩, 测试数据容量, 测试时间, 嵌入式确定性测试(EDT), 自动测试向量生成(ATPG)

Abstract: To realize test patterns compression more efficient in integrated circuit Design for Test (DFT), and reduce test data volume and test time, the S13207, S15850, S38417 and S38584 benchmark circuits were analyzed using Embedded Deterministic Test (EDT) scan test compression scheme. By studying the factors that affect test compression such as test patterns and shift cycles, a scan test compression circuit optimization method was proposed with constant test ports and constant compression ratios. The results show that the benchmark circuits have a good compression effect when the number of test ports was set to 2 and the compression ratio was set to 12, 14, 16 and 24 respectively. Compared with the traditional Automatic Test Pattern Generation (ATPG), stuck-at faults test data volume was reduced by 3.9-6.4 times, and test time was reduced by 3.8-6.2 times; transition faults test data volume was reduced by 4.1-5.4 times, and test time was reduced by 3.8-5.2 times. By changing the number of test ports and compression ratios, this method discusses various factors that affect test compression and gives an optimized scheme for the scan test circuit compression design. It improved the efficiency of the scan compression test. This method was verified in a large-scale circuit, and the result shows that it can be applied to the design of integrated circuit scan test compression.

Key words: Design for Test(DFT), scan test compression, test data volume, test time, Embedded Deterministic Test(EDT), Automatic Test Pattern Generation(ATPG)

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