一种新型低功耗SRAM读写辅助电路设计

doi:10.13700/j.bh.1001-5965.2019.0533

北京航空航天大学学报 ›› 2020, Vol. 46 ›› Issue (8): 1618-1624.doi: 10.13700/j.bh.1001-5965.2019.0533

• 论文 • 上一篇

一种新型低功耗SRAM读写辅助电路设计

郭春成¹, 郝旭丹², 陈霏¹

1. 天津大学微电子学院, 天津 300072;
2. 中芯国际集成电路制造有限公司, 北京 100176

收稿日期:2019-10-09 发布日期:2020-08-27
通讯作者: 郭春成 E-mail:3013204294@tju.edu.cn
作者简介:郭春成男,硕士研究生。主要研究方向:低功耗SRAM设计。
郝旭丹男,硕士,高级工程师。主要研究方向:存储器设计。
陈霏男,博士,副教授。主要研究方向:CMOS太赫兹热探测器机理、关键技术研究及用于无线助听器的低功耗超宽带收发机关键技术。
基金资助:
国家自然科学基金（61501323）

Design of a novel read and write assisted circuit in low power SRAM

GUO Chuncheng¹, HAO Xudan², CHEN Fei¹

1. School of Microelectronics, Tianjin University, Tianjin 300072, China;
2. Semiconductor Manufacturing International Corporation, Beijing 100176, China

Received:2019-10-09 Published:2020-08-27
Supported by:
National Natural Science Foundation of China (61501323)

摘要/Abstract

摘要： 针对低电压下静态随机存储器（SRAM）出现的读写性能损失的问题，设计了一种应用于低功耗SRAM的两步控制（DSC）的字线电压辅助电路技术，可以同时实现读和写辅助的功能，降低SRAM的最小工作电压从而降低功耗。写辅助通过字线开启前段的字线过驱（WLOD）实现，提高写数据速度和写阈值（WM）；读辅助通过字线开启后段的字线欠驱（WLUD）实现，降低静态噪声，提高稳定性。通过在28 nm互补金属氧化物半导体（CMOS）工艺下，对256 Kbit SRAM进行前仿和后仿仿真验证，结果表明相比于传统结构，应用DSC字线电压技术的SRAM的最小工作电压降低100 mV，写时间减小10%，静态功耗降低30%，版图面积增大4%。

关键词: 静态随机存储器(SRAM), 低功耗, 两步控制(DSC), 最小工作电压, 静态功耗

Abstract: In order to solve the problem of read and write performance loss in Static Random-Access Memory (SRAM) under low voltage, a novel Dual-Step Control (DSC) word-line voltage technique for low power SRAM is designed, which can simultaneously realize read and write performance and reduce the minimum operation voltage of SRAM. Thus the power consumed is reduced. Write-assist implementation uses the Word-Line Over Drive (WLOD) at the beginning of the word-line to reduce the write access time and improve Write Margin (WM). And read-assist implementation uses the Word-Line Under Drive (WLUD) after the WLOD to reduce static noise and increase the stability. A 256 Kbit SRAM pre-sim and post-sim simulation, which is designed in 28 nanometer Complementary Metal Oxide Semiconductor (CMOS) process, demonstrates that DSC-SRAM lowers the minimum operation voltage by 100 mV, reduces the write access time by 10%, decreases the static power by 30%, and increases its layout area by 4%, compared to the conventional SRAM structure.

Key words: Static Random-Access Memory(SRAM), low power, Dual-Step Control(DSC), minimum operation voltage, static power

中图分类号:

TN47

郭春成, 郝旭丹, 陈霏. 一种新型低功耗SRAM读写辅助电路设计[J]. 北京航空航天大学学报, 2020, 46(8): 1618-1624.

GUO Chuncheng, HAO Xudan, CHEN Fei. Design of a novel read and write assisted circuit in low power SRAM[J]. Journal of Beijing University of Aeronautics and Astronautics, 2020, 46(8): 1618-1624.

参考文献

[1] MARINISSEN E J,PRINCE B,KEITEL-SCHULZ D,et al.Challenges in embedded memory design and test[C]//Proceedings of Design,Automation and Test in Europe.Piscataway:IEEE Press,2005:722-727.
[2] ZHANG K.Embedded memories for nano-scale VLSIs[M].Berlin:Springer,2009:91-93.
[3] BHASKAR A.Design and analysis of low power SRAM cells[C]//2017 Innovations in Power and Advanced Computing Technologies.Piscataway:IEEE Press,2018:1-5.
[4] TAKASHIMA D,ENDO M,SHIMAZAKI K,et al.A 7T-SRAM with data-write technique by capacitive coupling[J].IEEE Journal of Solid-State Circuits,2019,54(2):596-605.
[5] GROVER A,VISWESWARAN G S,PARTHASARATHY C R,et al.A 32 kb 0.35-1.2 V,50 MHz-2.5 GHz bit-interleaved SRAM with 8T SRAM cell and data dependent write assist in 28 nm UTBB-FDSOI CMOS[J].IEEE Transactions on Circuits and Systems I:Regular Papers,2017,64(9):2438-2447.
[6] SAXENA S,MEHRA R.Low-power and high-speed 13T SRAM cell using FinFETs[J].IET Circuits Devices & Systems,2017,11(3):250-255.
[7] DUAN C,GOTTERBA A J,SINANGIL M E,et al.Energy-efficient reconfigurable SRAM:Reducing read power through data statistics[J].IEEE Journal of Solid-State Circuits,2017,52(10):1-9.
[8] PAVLOV A.CMOS SRAM circuit design and parametric test in nano-scaled technologies[M].Berlin:Springer,2008:2703-2711.
[9] NHO H,KOLAR P,HAMZAOGLU F,et al.A 32 nm high-k metal gate SRAM with adaptive dynamic stability enhancement for low-voltage operation[C]//IEEE International Solid-State Circuits Conference.Piscataway:IEEE Press,2010:76-84.
[10] SONG T,RIM W,PARK S,et al.A 10 nm FinFET 128 Mb SRAM with assist adjustment system for power,performance,and area optimization[J].IEEE Journal of Solid-State Circuits,2017,52(1):240-249.
[11] LIEN N C,CHU L W,CHEN C H,et al.A 40 nm 512 kb cross-point 8T pipeline SRAM with binary word-line boosting control,ripple bit-line and adaptive data-aware write-assist[J].IEEE Transactions on Circuits and Systems I:Regular Papers,2017,61(12):3416-3425.
[12] CHEN Y H,CHAN W M,WU W C,et al.A 16 nm 128 Mb SRAM in high-k metal-gate FinFET technology with write-assist circuitry for low-VMIN applications[J].IEEE Journal of Solid-State Circuits,2015,50(1):170-177.
[13] SINANGIL M E,POULTON J W,FOJTIK M R,et al.A 28 nm 2 Mbit 6T SRAM with highly configurable low-voltage write-ability assist implementation and capacitor-based sense-amplifier input offset compensation[J].IEEE Journal of Solid-State Circuits,2015,50(2):557-567.
[14] CHANG M F,CHEN C F,CHANG T H,et al.A compact-area low-VDDmin 6T SRAM with improvement in cell stability,read speed,and write margin using a dual-split-control-assist scheme[J].IEEE Journal of Solid-State Circuits,2017,52(9):2498-2514.
[15] SINANGIL M E,MAIR H,CHANDRAKASAN A P.A 28 nm high-density 6T SRAM with optimized peripheral-assist circuits for operation down to 0.6V[C]//IEEE International Solid-State Circuits Conference.Piscataway:IEEE Press,2011:260-261.

一种新型低功耗SRAM读写辅助电路设计

Design of a novel read and write assisted circuit in low power SRAM

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