Evaluating SEU effects in SRAM-based FPGA with bit-by-bit upset fault injection
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摘要: 针对SRAM(Static Random Access Memory)型FPGA(Field Programmable Gate Array)空间应用的可靠性评测问题,提出一种逐位翻转的故障注入试验方法,利用动态重配置技术,通过检测逻辑电路设计配置存储单元中的单粒子翻转敏感位数量和位置,可计算出动态翻转截面和失效率,绘出可靠度变化曲线.分别对采用TMR(Triple Modular Redundancy)防护设计的和未采用TMR防护设计的SRAM型FPGA乘法器模块进行了故障注入试验,验证了得到的敏感位位置的正确性,并计算出各自的可靠性参数和曲线.Abstract: Static random access memory (SRAM)-based field programmable gate arrays (FPGAs) are extremely sensitive to single event upsets (SEUs) induced by radiation particles. In order to evaluate the dependability of the obtained designs, a bit-by-bit upset fault injection methodology based on run-time reconfiguration was proposed. The methodology can detect the sensitive bits in various logic designs. The configuration memories’ dynamic cross section, failure rate and reliability change curve can be counted with the number of sensitive bits. The reliability parameters and curves of triple modular redundancy (TMR) multiplier and non-TMR multiplier were obtained with this method, and the correctness of sensitive bits was validated.
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Key words:
- fault injection /
- single event upset /
- run-time reconfiguration
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