基于EDT的扫描测试压缩电路优化方法

李松; 赵毅强; 叶茂

doi:10.13700/j.bh.1001-5965.2019.0530

基于EDT的扫描测试压缩电路优化方法

doi: 10.13700/j.bh.1001-5965.2019.0530

李松^{1, 2, ,},
赵毅强^{1, 2},
叶茂^{1, 2}

1.
天津大学微电子学院, 天津 300072
2.
天津市成像与感知微电子技术重点实验室, 天津 300072

详细信息

作者简介:
李松  男, 硕士研究生。主要研究方向:集成电路可测试性设计

赵毅强  男, 博士, 教授, 博士生导师。主要研究方向:射频集成电路设计、混合信号集成电路设计、集成电路安全检测技术、安全存储芯片设计、抗攻击技术、光电检测与成像系统设计、传感器系统设计

叶茂  男, 博士, 副教授, 硕士生导师。主要研究方向:混合信号集成电路设计

通讯作者:
李松. E-mail:keepls_833@163.com

中图分类号: TN47
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出版历程
- 收稿日期: 2019-09-29
- 录用日期: 2020-01-15
- 网络出版日期: 2020-08-20

Optimization method of scan test compression circuit based on EDT

LI Song^{1, 2
, ,},
ZHAO Yiqiang^{1, 2},
YE Mao^{1, 2}

1.
School of Microelectronics, Tianjin University, Tianjin 300072, China
2.
Tianjin Key Laboratory of Imaging and Sensing Microelectronic Technology, Tianjin 300072, China

More Information

Corresponding author: LI Song. E-mail:keepls_833@163.com

摘要

摘要:
为了在集成电路可测试性设计（DFT）中实现更有效的测试向量压缩，减少测试数据容量和测试时间，采用嵌入式确定性测试（EDT）的扫描测试压缩方案分别对S13207、S15850、S38417和S38584基准电路进行了优化分析，通过研究测试向量和移位周期等影响测试压缩的因素，提出了固定测试端口和固定压缩率的扫描测试压缩电路优化方法。结果表明，在测试端口数量都为2，压缩率分别为12、14、16和24时具有较好的压缩效果，与传统自动测试向量生成（ATPG）相比，固定故障的测试数据容量减小了3.9~6.4倍，测试时间减少了3.8~6.2倍，跳变延时故障的测试数据容量减少了4.1~5.4倍，测试时间减少了3.8~5.2倍。所提方法通过改变测试端口数和压缩率的方式讨论了多种影响测试压缩的因素，给出扫描测试压缩电路的优化设计方案，提高了压缩效率，并对一个较大规模电路进行了仿真验证，可适用于集成电路的扫描测试压缩设计。
- 可测试性设计(DFT) /
- 扫描测试压缩 /
- 测试数据容量 /
- 测试时间 /
- 嵌入式确定性测试(EDT) /
- 自动测试向量生成(ATPG)
Abstract:
To realize test patterns compression more efficient in integrated circuit Design for Test (DFT), and reduce test data volume and test time, the S13207, S15850, S38417 and S38584 benchmark circuits were analyzed using Embedded Deterministic Test (EDT) scan test compression scheme. By studying the factors that affect test compression such as test patterns and shift cycles, a scan test compression circuit optimization method was proposed with constant test ports and constant compression ratios. The results show that the benchmark circuits have a good compression effect when the number of test ports was set to 2 and the compression ratio was set to 12, 14, 16 and 24 respectively. Compared with the traditional Automatic Test Pattern Generation (ATPG), stuck-at faults test data volume was reduced by 3.9-6.4 times, and test time was reduced by 3.8-6.2 times; transition faults test data volume was reduced by 4.1-5.4 times, and test time was reduced by 3.8-5.2 times. By changing the number of test ports and compression ratios, this method discusses various factors that affect test compression and gives an optimized scheme for the scan test circuit compression design. It improved the efficiency of the scan compression test. This method was verified in a large-scale circuit, and the result shows that it can be applied to the design of integrated circuit scan test compression.
- Design for Test(DFT) /
- scan test compression /
- test data volume /
- test time /
- Embedded Deterministic Test(EDT) /
- Automatic Test Pattern Generation(ATPG)

HTML全文

图 1 EDT压缩结构^[11]

Figure 1. Structure of EDT compression^[11]

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图 2 EDT压缩逻辑与传统ATPG对比

Figure 2. EDT compression logic compared with traditional ATPG

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图 3 EDT压缩设计流程

Figure 3. EDT compression design flow

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图 4 EDT压缩优化方法

Figure 4. EDT compression optimization method

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图 5 ISCAS’89基准电路故障覆盖率损失

Figure 5. Fault coverage loss of ISCAS'89 benchmark circuits

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图 6 测试向量数量和扫描链测试向量占比

Figure 6. Number of test patterns and scanchain test patterns percentage

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图 7 移位周期数和EDT额外移位周期占比

Figure 7. Shift cycles and EDT additional cycles percentage

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图 8 固定测试端口数分析结果

Figure 8. Analysis results by constant number of test ports

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图 9 固定压缩率分析结果

Figure 9. Analysis results by constant compression ratio

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表 1 压缩分析参数变化

Table 1. Change of compression analysis parameters

测试结果	固定测试端口	固定压缩率
P	增加	基本不变
P′_c	增加	增加
C	先减少后增加	减少
C′_a	增加	增加
FC	减少	基本不变
V′	先减少后增加	增加
T′	先减少后增加	减少

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表 2 基准电路参数变化

Table 2. Change of benchmark circuits parameters

基准电路		G	FFs	L	F_au
S13207	Bef.	3 404	447	224	12 630
S13207	Aft.	4 009	507	19	14 894
S15850	Bef.	4 168	448	224	16 194
S15850	Aft.	4 874	508	14	19 198
S38417	Bef.	12 690	1 484	742	46 692
S38417	Aft.	13 429	1 550	47	51 892
S38584	Bef.	12 906	1 235	620	51 306
S38584	Aft.	14 126	1 305	26	56 018

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表 3 固定故障测试压缩优化数据对比

Table 3. Comparison of stuck-at faults test compression optimization data

基准电路	FC/%		P		P′_c/%	C/10³		C′_a/%	V′/KB		Div. (V′)	T′/(10^-2μs)		Div. (T′)
基准电路	Bef.	Aft.	Bef.	Aft.	P′_c/%	Bef.	Aft.	C′_a/%	Bef.	Aft.	Div. (V′)	Bef.	Aft.	Div. (T′)
S13207	99.81	98.13	130	176	12.5	29.1	6.1	43.0	58.2	12.0	4.9	29.1	6.1	4.7
S15850	99.94	98.72	144	295	14.0	32.3	8.5	44.2	64.5	16.5	3.9	32.3	8.5	3.8
S38417	100	99.05	156	329	11.6	115.8	21.0	25.0	231.5	41.5	5.6	115.8	21.0	5.5
S38584	99.91	99.40	161	374	10.4	99.8	16.1	37.3	199.6	31.4	6.4	99.8	16.1	6.2
SS	98.16	98.14	4 267	5 597	0.7	56 153.7	2 776.1	7.9	112 298.9	5 541.0	20.3	56 153.7	2 776.1	20.2

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表 4 跳变延时故障测试压缩优化数据对比

Table 4. Comparison of transition faults test compression optimization data

基准电路	FC/%		P		P′_c/%	C/10³		C′_a/%	V′/KB		Div. (V′)	T′/(10^-2μs)		Div. (T′)
基准电路	Bef.	Aft.	Bef.	Aft.	P′_c/%	Bef.	Aft.	C′_a/%	Bef.	Aft.	Div. (V′)	Bef.	Aft.	Div. (T′)
S13207	82.31	81.27	200	253	8.7	44.8	9.1	41.9	89.6	17.2	5.2	44.8	9.1	4.9
S15850	76.34	75.93	175	332	12.0	39.2	10.2	43.8	78.4	19.3	4.1	39.2	10.2	3.8
S38417	94.21	93.63	255	734	5.2	189.2	47.6	24.7	378.4	92.5	4.1	189.2	47.6	4.0
S38584	81.10	80.14	319	874	4.5	197.8	38.4	36.4	395.6	73.4	5.4	197.8	38.4	5.2
SS	84.09	82.80	6 830	8 790	0.4	89 889.6	4 368.5	7.3	179 751.9	8 702.1	20.7	89 889.6	4 368.5	20.6

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