北京航空航天大学学报 ›› 2006, Vol. 32 ›› Issue (01): 74-78.

• 论文 • 上一篇    下一篇

多媒体流处理器中缓冲器的体系结构设计

王光, 沈绪榜   

  1. 西安微电子技术研究所, 西安 710054
  • 收稿日期:2005-02-04 出版日期:2006-01-31 发布日期:2010-09-20
  • 作者简介:王 光(1973-), 男, 山东烟台人, 博士生, Jack.wang.guang@tom.com.
  • 基金资助:

    "十五"国防863计划资助项目(2002AA714022)

Design of buffer architecture for multi-media stream microprocessor

Wang Guang, Shen Xubang   

  1. Xi'an Microelectronic Technology Institute, Xi'an 710054, China
  • Received:2005-02-04 Online:2006-01-31 Published:2010-09-20

摘要: 传统微处理器体系结构不能很好地匹配媒体处理应用的特点.针对处理器与存储器之间日益增长的性能间隙问题,分析了传统微处理器对媒体处理应用的通讯瓶颈;通过分析Cache存储器的特点,得出了传统的Cache结构并不适合现代媒体处理应用的结论,讨论了目前针对处理器通讯瓶颈的一些解决办法;提出了一种以大容量流寄存器堆替代Cache作为中间缓冲器,并能适合于媒体处理应用的金字塔存储层次体系结构设计.该体系结构具有三级并行数据带宽存储层次,即片外SDRAM、全局寄存器堆和局部寄存器堆.三级并行存储层次所能提供的带宽依次提高一个数量级,带宽之比为1∶16∶256,从而可以有效地支持卫星遥感图像预处理对数据带宽的需求.

Abstract: The characteristics of media processing applications are poorly matched to conventional microprocessor architectures. The growing processor-memory performance gap was solved. The communication bottlenecks of traditional microprocessor, which is used for media processing application, were discussed. It was concluded that the traditional Cache architecture does not adapt to the modern media processing application by analyzing the characteristics of Cache memory. Some current schemes used to solve the communication bottlenecks were discussed. A new architecture design of pyramid memory hierarchy was brought forward, which substituted the larger stream register files for Cache as the medial buffers and could adapt to media processing applications. This architecture provided a three-tiered parallel data bandwidth hierarchy, including memory bandwidth, global register bandwidth, and local register bandwidth, with a ratio of 1∶16∶256. With this bandwidth scaling, the bandwidth requirements of satellite remote sensing image pretreatment may be efficiently matched.

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