An efficient partially parallel decoder architecture suited for multi-rate low density parity check(LDPC) codes was presented. Algorithmic transformation and architectural level optimization were incorporated to reduce the critical path. The check node updating units (CNU) and the variable node updating units (VNU) were divided several smaller parts, which are dynamically grouped under different code rate according to the row the column weights of check matrix. This method brings in great redundancy reduction of CNU and VNU, and the decoding rate was increased significantly for the small row-weight (column-weight) codes. Based on the proposed architectures, a 7k-lenth multi-rate LDPC code of rate 0.4, 0.6 and 0.8 decoder was described using verilog hardware design language and implemented on Altera field programmable gate array (FPGA) Stratix EP1S80. The implementation results show that this multi-rate decoder is just 12% larger in logic core size than a single rate decoder. Compared with the conventional partially parallel decoder, this decoder increases the throughput of rate 0.4 code is increased by 100% and rate 0.6 code by 50% without any hardware resource incensement and performance loss.
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