北京航空航天大学学报 ›› 2015, Vol. 41 ›› Issue (10): 1813-1820.doi: 10.13700/j.bh.1001-5965.2014.0809

• 电磁理论与应用 • 上一篇    下一篇

热效应布局下的缓冲器插入时序优化方法

王新胜1, 韩良1, 喻明艳2   

  1. 1. 哈尔滨工业大学信息与电气工程学院, 威海 264209;
    2. 浙江大学宁波理工学院, 宁波 315100
  • 收稿日期:2014-12-23 修回日期:2015-02-12 出版日期:2015-10-20 发布日期:2015-11-02
  • 通讯作者: 韩良(1969-),男,吉林榆树人,副教授,hanliang@hit.edu.cn,主要研究方向为大规模集成电路设计. E-mail:hanliang@hit.edu.cn
  • 作者简介:王新胜(1978-),男,山东威海人,讲师,xswang@hit.edu.cn
  • 基金资助:
    国家自然科学基金(61201307)

Thermal aware floor planning timing optimal method for buffer insertion

WANG Xinsheng1, HAN Liang1, YU Mingyan2   

  1. 1. Shool of Information and Electrical Engineering, Harbin Institute of Technology, Weihai 264209, China;
    2. Ningbo Institute of Technology, Zhejiang University, Ningbo 315100, China
  • Received:2014-12-23 Revised:2015-02-12 Online:2015-10-20 Published:2015-11-02

摘要: 随着集成电路的集成度越来越高,芯片的发热量越来越大且其内部温度呈不均匀分布,这会影响关键路径的传播延时,进而影响基于缓冲器插入的关键路径性能.提出了一种考虑芯片热效应布局优化的缓冲器插入时序优化方法,在版图设计的早期估计芯片的热分布和温度分布并且把其应用到版图布局优化和RC延时模型中.同时利用模拟退火算法基于热分布调整并优化布局,最后在最优布局下利用提出的缓冲器插入模型和快速插入算法进行时序优化.仿真结果表明相对于不考虑温度效应布局优化的缓冲器插入方法,缓冲器插入延时优化方法能有效降低最坏延时和缓冲器插入数目,最坏延时比传统方法降低9%~18%,比文献已经提出的最好方法降低5%~7%,缓冲器插入数比其少10~20个.

关键词: 大规模集成电路, 布局规划, 缓冲器插入, 互连线, 模拟退火算法

Abstract: With the integration degree of integrated circuit (IC) is increasingly high, the heat on a chip is also growing, which leads to an uneven temperature distribution intra-die and affects the propagation delay of the critical path thereby affecting the performance of buffer insertion path. A buffer insertion timing optimization method which considered the heat distribution condition optimization floor-planning was proposed. It estimates the temperature and heat distribution of chip in the early stages of layout design and is applied to layout optimization floor-planning. The thermal aware floor planning based on simulated annealing algorithm was used to adjust and optimize planning, and then we made an optimization for timing by proposed buffer insertion model and fast buffer insertion algorithm. Simulation results show that the use of the proposed buffer insertion delay optimization method can effectively reduce the worst delay and the number of buffer insertion, worst delay is 9%-18% lower than traditional methods, 5%-7% lower than the best method shown in reference, and the insertion buffer numbers are 10 to 20 less than its.

Key words: very large scale integrated circuit, floor planning, buffer insertion, interconnect, simulated annealing algorithm

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