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�������պ����ѧѧ�� 2009, Vol. 35 Issue (11) :1339-1343    DOI:
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FPGA-based hardware-efficient architecture for variable block-size motion estimation
Wang Rui, Jiang Hongxu, Li Bo*
School of Computer Science and Technology, Beijing University of Aeronautics and Astronautics, Beijing 100191, China

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ժҪ ��Կɱ�ߴ���˶�����(VBSME,Variable Block-Size Motion Estimation)��Ӳ���ṹ���ֳ��ɱ��������(FPGA, Field Programmable Gate Array)��ʵ��ʱ������Դ�����ٶ���������,�����һ��������ٶ��Ż���VBSMEӲ���ṹ.����,���Բ��ۼӺ�(SAD,Sum of Absolute Differences)�ļ�����û�������洢��(RAM,Random Access Memory)���ۼӼ��㷽ʽ,�Ȼ��ڼĴ����ϲ��ķ�ʽ��ʡ��������������ٶ�;ͨ�����������Ƚ����������߽ṹ,��ǿ�˶��SADֵ�ıȽ�����,���ܸ�Ч��ʵ�ֶԲ��ֲ��ų��㷨(PDE,Partial Difference Elimination)��֧��.����Virtex-II��FPGA����,���ṹ������2�N261��slice,ʱ��Ƶ�ʴﵽ164�NMHz,����������Ϊ16×16ʱ��ʵʱ��������ʽ����Ƶ.��ͬ��������,��Ƶ�����ɼ���77%,�ٶ�����218%,FPGA��Ӳ��Ч����������.
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Abstract�� To improve the hardware efficiency of the FPGA-based(field programmable gate array based)architecture for variable block-size motion estimation, a novel architecture was proposed, which was optimized in both area and speed. This architecture introduced RAM-based SAD(sum of absolute differences) accumulators, which had better performance than register-based combiner in both area and speed. To improve the speed of SADs’ comparison and support partial difference eliminating algorithm, the architecture adopted a systolic comparing chain, which substituted for the bus-based comparator used in former designs. Based on Virtex-II family FPGA from Xilinx Inc., the proposed architecture consumed only 2�N261 slices, with the clock frequency as high as 164�NMHz. It means that the architecture could process standard-definition format video with 16×16 search window in real-time. Compared with similar designs, the architecture could save the area by 77% and increase the speed by 218%.
Keywords�� video coding   VBSME(variable block-size motion estimation)   hardware architecture   FPGA(field programmable gate array)     
Received 2008-11-11;


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�� ��, ������, �� ��.����FPGA�Ŀɱ�ߴ���˶����Ƹ�Ч�ṹ[J]  �������պ����ѧѧ��, 2009,V35(11): 1339-1343
Wang Rui, Jiang Hongxu, Li Bo.FPGA-based hardware-efficient architecture for variable block-size motion estimation[J]  JOURNAL OF BEIJING UNIVERSITY OF AERONAUTICS AND A, 2009,V35(11): 1339-1343
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