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�������պ����ѧѧ�� 2009, Vol. 35 Issue (10) :1237-1240    DOI:
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Efficient architecture design for AVS de-blocking loop filter
Liu Rongke, Yu Peng*
School of Electronics and Information Engineering, Beijing University of Aeronautics and Astronautics, Beijing 100191, China

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Abstract�� In order to meet the requirements in the real time decoding of high definition(HD) video, an efficient very large-scale integration(VLSI) architecture proper for de-blocking loop filter in audio video coding standard(AVS) was presented. The 8×8 blocks were divided into 4×4 blocks for filtering operations. After centralized process of 4×4 block boundaries, data and filtering operations were performed at the same time by improving filtering order. This architecture can increase the efficiency of pipelining and operating data in the SRAM, thereby highly reducing the total clock cycles of filtering process. Experiment results show that only 196 clock cycles are needed to finish filtering a macro-block for de-blocking filter in AVS. The processing speed increases by 50%. When the maximum frequency is 100 MHz, the real time decoding of HD video can be achieved in this architecture.
Keywords�� video signal processing   de-blocking filter   real-time decoding   HD video   VLSI circuits     
Received 2008-10-13;
About author: ���ٿ�(1973-),��,����������,������,rongke_liu@buaa.edu.cn.
���ٿ�, �� ��.��ЧAVS��·�˲����ṹ���[J]  �������պ����ѧѧ��, 2009,V35(10): 1237-1240
Liu Rongke, Yu Peng.Efficient architecture design for AVS de-blocking loop filter[J]  JOURNAL OF BEIJING UNIVERSITY OF AERONAUTICS AND A, 2009,V35(10): 1237-1240
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