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�������պ����ѧѧ�� 2009, Vol. 35 Issue (6) :678-682    DOI:
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�� ��, ������, �� ��*
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Novel optimized implementation of CABAC hardware encoder
Wang Rui, Jiang Hongxu, Li Bo*
School of Computer Science and Technology, Beijing University of Aeronautics and Astronautics, Beijing 100191, China

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ժҪ Ϊ�˽������������Ӧ����������������(CABAC,Context-based Adaptive Binary Arithmetic Coder)Ӳ��ʵ��������������ߵ�����,����˻�����������̬���Եĵ�·�Ż�����.ͨ�������㷨��������ģ��,��ȡ������Ӳ��ʵ�����ܵ�������������·.��������Ļ�·,����3���������ڲ�ͬ���ӻ�·���¾��в�ͬ�������ڵ������ı���,�����ʱ��Ƶ�ʺ�������;�����ֽڴ����·,ͨ����ȡһ��ɼ򻯵�·�ṹ������Ԫ��,��Ϊ֮����������·,�����˻�·�Ĵ����ٶ�.�����������������Ի����ĵ�·�Ż��ֶ�,���ʵ�����ֳ��ɱ��������(FPGA,Field-Programmable Gate Array)ƽ̨��Ƶ�ʿɴ�309�NMHz,����ÿ��ʱ�����ڴ���һ���������.
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Abstract�� To improve the throughput of hardware architecture for CABAC(context-based adaptive binary arithmetic coder), the optimization methods based on dynamic properties of dataflow were adopted. By building the dataflow model of CABAC algorithm, four inevitable loops brought by hardware implementation were abstracted and isolated, and the potential bottle-neck loops were examined and optimized. For the context-loop, three assistant sub-loops with different iteration cycle were used to update the context variables needed by the data elements with different dependency-cycle. For the byte-package loop, a special kind of data elements was discriminated, which could simplify the circuit architecture and speed up the clock frequency. By building a dedicated fast by-pass channel for these special data elements, the throughput of byte-package loop was improved. Also benefiting from other basic optimization methods, the entire CABAC hardware architecture could achieve 309 MHz on FPGA(field-programmable gate array) platform and process one binary symbol per clock cycle.
Keywords�� arithmetic coding   context-based adaptive binary arithmetic coder   hardware architecture   field-programmable gate array     
Received 2008-04-22;


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�� ��, ������, �� ��.CABAC����������Ӳ���Ż�ʵ��[J]  �������պ����ѧѧ��, 2009,V35(6): 678-682
Wang Rui, Jiang Hongxu, Li Bo.Novel optimized implementation of CABAC hardware encoder[J]  JOURNAL OF BEIJING UNIVERSITY OF AERONAUTICS AND A, 2009,V35(6): 678-682
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