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�������պ����ѧѧ�� 2008, Vol. 34 Issue (10) :1177-1181    DOI:
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2-D parallel memory architecture for video processor
Zhu Di, Shen Gongxun*
School of Astronautics, Beijing University of Aeronautics and Astronautics, Beijing 100191, China

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Abstract�� Video codec has a very high computation complexity and features intensive vector accesses to memory. A 2-D parallel memory scheme based on linear skewing scheme was proposed. The memory scheme can be combined with simple instruction multiple data (SIMD) vector processor to address the computation challenge of video. The address generation logic and scheme-s micro architecture were analyzed. The scheme uses a data rotation unit to permute data element to form a vector. This method simplified data permutation network which is the bottleneck of most parallel memory schemes. The performance difference between parallel memory and traditional memory were also compared. The kernel module of H.264/AVC such as motion estimation, de-blocking filter and interpolation were investigated based on the proposed memory scheme.
Keywords�� video coding   memory architecture   very large-scale integration(VLSI)     
Received 2007-11-12;
About author: �� ��(1977-),��,ɽ��������,��ʿ��,andy_zhudi@yahoo.com.cn.
�� ��, �깦ѫ.һ������ʸ����Ƶ�������IJ��д洢�ṹ[J]  �������պ����ѧѧ��, 2008,V34(10): 1177-1181
Zhu Di, Shen Gongxun.2-D parallel memory architecture for video processor[J]  JOURNAL OF BEIJING UNIVERSITY OF AERONAUTICS AND A, 2008,V34(10): 1177-1181
http://bhxb.buaa.edu.cn//CN/     ��     http://bhxb.buaa.edu.cn//CN/Y2008/V34/I10/1177
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