北京航空航天大学学报 ›› 2007, Vol. 33 ›› Issue (12): 1440-1443.

• 论文 • 上一篇    下一篇

一种基于FPGA的超高速32k点FFT处理器

李伟,孙进平,王俊,李少洪   

  1. 北京航空航天大学 电子信息工程学院, 北京 100083
  • 收稿日期:2006-12-15 出版日期:2007-12-31 发布日期:2010-09-17
  • 作者简介:李 伟(1975-),男,湖南邵阳人,博士生,windriver@126.com.

Implementation of 32k points ultra high speed FFT processor based on FPGA devices

Li Wei, Sun Jinping, Wang Jun, Li Shaohong   

  1. School of Electronics and Information Engineering, Beijing University of Aeronautics and Astronautics, Beijing 100083, China
  • Received:2006-12-15 Online:2007-12-31 Published:2010-09-17

摘要: 采用FPGA(Field Programmable Gate Arrays)实现了一个超高速的32k点的流水线FFT(Fast Fourier Transform)处理器.FPGA的工作频率为125MHz,可以处理连续的1Gs/s(1 Giga-samples per second)的复数数据.该FFT处理器主要基于二维分解算法,采用MDF(Multi-path Delay Feedback)流水线结构,并结合MDC(Multi-path Delay Commutator)及SDF(Single-path Delay Feedback)结构的特点.处理器的内存资源消耗相对MDC结构有所减少,而运算速度相对SDF结构有所提高.建立了处理器的算法和设计模型,并根据模型对处理器的3个组成模块进行了优化以减小资源消耗.利用VHDL语言在Xilinx ISE工具上进行了设计,FPGA的布局布线结果验证了设计的可行性.

Abstract: An ultra high speed 32k point pipelined fast Fourier transform (FFT) processor was designed with FPGA (field programmable gate arrays) implementation. The processor can operate at 125 MHz and is able to handle a continuous input complex data stream of 1 Giga-samples per second. The FFT processor is based on MDF(multi-path delay feedback) structure which combines the features of the SDF(single-path delay feedback) and MDC(multi-path delay commutator) architectures. The memory cost of the processor was decreased compared with the MDC architectures while the speed is higher than the SDF architectures. The algorithm and design model for the processor was established and the three modules of the processor according to the design model were optimized to decrease resource cost. The design was implemented with the the Xilinx ISE development tool using VHDL and was verified with the FPGA place and router results.

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