北京航空航天大学学报 ›› 2007, Vol. 33 ›› Issue (04): 495-499.

• 论文 • 上一篇    下一篇

二级进位跳跃加法器的优化方块分配

崔晓平, 王成华   

  1. 南京航空航天大学 信息科学与技术学院, 南京 210016
  • 收稿日期:2006-09-19 出版日期:2007-04-30 发布日期:2010-09-19
  • 作者简介:崔晓平(1962-),女,安徽巢湖人,讲师,cuixp126@126.com

Optimal block distribution in carry-skip adders

Cui Xiaoping, Wang Chenghua   

  1. College of Information Science and Technology,Nanjing University of Aeronautics and Astronautics, Nanjing 210016, China
  • Received:2006-09-19 Online:2007-04-30 Published:2010-09-19

摘要: 提出了一种新的获得二级进位跳跃加法器优化方块分配的算法.根据该算法,在确定最坏路径延时的前提下,首先获得该延时下加法器最大的优化方块尺寸,然后确定任意位二级进位跳跃加法器的优化方块尺寸.优化方块分配的进位跳跃加法器可以缩短关键路径的延时.给出了加法器门级延时、复杂度的分析,分析结果显示,通过优化方块分配,可以以较少的额外门电路获得快速的进位跳跃加法器.该加法器已用PSPICE 仿真工具进行了功能验证和仿真.PSPICE 仿真分析表明,所提出的二级优化方块分配进位跳跃加法器的速度优于等尺寸二级进位跳跃加法器.

Abstract: A new type of optimal block distribution algorithm of two level carry-skip adder was described to determine optimal block distribution sizes. According to this algorithm, with the given total worst case delay, the maximum optimal block distribution sizes of the adder for that delay can be determined. It is simplified to obtain optimal block distribution of any desired adder sizes. The carry skip adder optimal block sizes can minimize critical path delay. The analysis of gate delay and complexity were provided. Although the two-level carry skip adder with optimal block distribution uses a few extra gates, it provides better speed than the adders with fixed size blocks. The adder has been functionally verified and simulated by using PSPICE. The simulation analysis of time delay reveals that the two-level optimal block distribution carry-skip adder can provide faster speed than the carry-skip adder with fixed size blokes.

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