Novel method of extraction for binary based on hardware
-
摘要: 一种适合于硬件的、普适的、开任意次方的方法,从左至右进行计算,首先得到开方结果的高位,最后得到低位.应用到FPGA(Field Programmable Gate Array)中,与查表结合,对不同的开方次数,模块修改非常方便,普适性较高.该方法消耗的时间与开方的次数呈线性关系.在对一个12bit数开三次方时,消耗的时间不足传统循环搜索法的50%,所消耗的存储空间不足传统的查表法的2%,并且存储空间上的优势在被开方位数越大的时候越明显.更重要的是,该方法所用的模块只需修改数据位宽和循环次数两处地方就可以提高到任意的精度.
-
关键词:
- 开方 /
- 硬件 /
- Verilog HDL
Abstract: A method of any order extraction, works from left to right, which is based on hardware and calculates out the most significant bit(MSB) of the result first and the least significant bit(LSB) last. While applied in field programmable gate array(FPGA), the method can combine with looking up table(LUT). Using this method, the occupying time is linear to the extraction order. While doing a 3 order extraction for a 12 bit data, the occupying time of this method is 50% less than the traditional searching method, and the occupying memory is only 2% that of traditional method of LUT. As the order of extraction grows, the superiority will be more obvious. More important, the module only need to be modified in 2 point, the precision can be improved as wanted.-
Key words:
- extraction /
- hardware /
- Verilog HDL
-
[1] Li Yamin, Chu Wanminn. Parallel-array implementations of a non-restoring square root algorithm // Computer Design: VLSI in Computers and Processors.Austin,TX:IEEE,1997: 690- 695 [2] 林志谋,卢贵主.一种适合FPGA实现的开平方算法[J].厦门大学学报,2006,45(2):199-201 Lin Zhimou,Lu Guizhu. A square root algorithm based on FPGA[J]. Journal of Xiamen University,2006,45(2):199-201(in Chinese) [3] Kincaid David, Cheney Ward.数值分析[M].王国荣译.北京:机械工业出版社,2005: 63-64 David Kincaid, Ward Cheney. Numeric analysis[M]. Translated by Wang Guorong. Beijing: China Machine Press,2005: 63-64(in Chinese) [4] Hungerfor T W.代数学[M].冯克勤译.湖南:湖南教育出版社,1985: 177 Hungerfor T W. Algebra[M].Translated by Feng Keqin. Hunan: Hunan Education Press,1985: 177(in Chinese) -
点击查看大图
计量
- 文章访问数: 3195
- HTML全文浏览量: 164
- PDF下载量: 2442
- 被引次数: 0
下载:
