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Volume 38 Issue 10
Oct.  2012
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Journal of Beijing University of Aeronautics and Astronautics  > 2012  >  38(10): 1285-1289.
Song Ningfang, Qin Jiaomei, Pan Xiong, et al. Evaluating SEU effects in SRAM-based FPGA with bit-by-bit upset fault injection[J]. Journal of Beijing University of Aeronautics and Astronautics, 2012, 38(10): 1285-1289. (in Chinese)
Citation: Song Ningfang, Qin Jiaomei, Pan Xiong, et al. Evaluating SEU effects in SRAM-based FPGA with bit-by-bit upset fault injection[J]. Journal of Beijing University of Aeronautics and Astronautics, 2012, 38(10): 1285-1289. (in Chinese)
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Evaluating SEU effects in SRAM-based FPGA with bit-by-bit upset fault injection

  • 1.

    School of Instrument Science and Opto-electronics Engineering, Beijing University of Aeronautics and Astronautics, Beijing 100191, China

  • 2. The Second Artillery Equipment Academy, Beijing 100085, China

  • Received Date: 07 Sep 2011
  • Publish Date: 30 Oct 2012
    Abstract
  • Static random access memory (SRAM)-based field programmable gate arrays (FPGAs) are extremely sensitive to single event upsets (SEUs) induced by radiation particles. In order to evaluate the dependability of the obtained designs, a bit-by-bit upset fault injection methodology based on run-time reconfiguration was proposed. The methodology can detect the sensitive bits in various logic designs. The configuration memories’ dynamic cross section, failure rate and reliability change curve can be counted with the number of sensitive bits. The reliability parameters and curves of triple modular redundancy (TMR) multiplier and non-TMR multiplier were obtained with this method, and the correctness of sensitive bits was validated.

     

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    • References(8)
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