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FDSOI背偏与体硅体偏电路的功耗性能对比

王剑 于芳 赵凯 李建忠 杨波 徐烈伟

王剑, 于芳, 赵凯, 等 . FDSOI背偏与体硅体偏电路的功耗性能对比[J]. 北京航空航天大学学报, 2018, 44(11): 2430-2436. doi: 10.13700/j.bh.1001-5965.2018.0142
引用本文: 王剑, 于芳, 赵凯, 等 . FDSOI背偏与体硅体偏电路的功耗性能对比[J]. 北京航空航天大学学报, 2018, 44(11): 2430-2436. doi: 10.13700/j.bh.1001-5965.2018.0142
WANG Jian, YU Fang, ZHAO Kai, et al. Comparison of power consumption and circuit performance between back bias in FDSOI and body bias in bulk silicon[J]. Journal of Beijing University of Aeronautics and Astronautics, 2018, 44(11): 2430-2436. doi: 10.13700/j.bh.1001-5965.2018.0142(in Chinese)
Citation: WANG Jian, YU Fang, ZHAO Kai, et al. Comparison of power consumption and circuit performance between back bias in FDSOI and body bias in bulk silicon[J]. Journal of Beijing University of Aeronautics and Astronautics, 2018, 44(11): 2430-2436. doi: 10.13700/j.bh.1001-5965.2018.0142(in Chinese)

FDSOI背偏与体硅体偏电路的功耗性能对比

doi: 10.13700/j.bh.1001-5965.2018.0142
详细信息
    作者简介:

    王剑  男, 博士研究生。主要研究方向:SOI工艺及相应电路设计、FPGA测试

    于芳  女, 研究员, 博士生导师。主要研究方向:SOI工艺及相应辐照机理、超大规模集成电路设计

    通讯作者:

    于芳, E-mail:yufang@ime.ac.cn

  • 中图分类号: TN402;TN710

Comparison of power consumption and circuit performance between back bias in FDSOI and body bias in bulk silicon

More Information
  • 摘要:

    针对功耗和工作频率对22 nm FDSOI背偏和28 nm体硅体偏电路的偏置能力进行对比和分析。以带有4级分频电路的65级环阵(RO)为例进行后仿真,后仿真结果表明,利用背偏技术的22 nm FDSOI环阵的输出频率可在57.8~206 MHz的范围内进行调节,相应的工作电流变化范围为24.4~90.4 μA;而利用体偏技术的28 nm体硅环阵的输出频率调节范围则为92.8~127 MHz,对应的工作电流变化范围为67.8~129 μA。对22 nm FDSOI工艺的环阵进行了实测,实测结果与仿真结果一致。分析认为,在功耗和性能2个方面,22 nm FDSOI电路的背偏调节能力优于28 nm体硅电路的体偏调节能力。

     

  • 图 1  体硅CMOS和厚膜SOI工艺的体偏

    Figure 1.  Body bias in bulk CMOS and thick SOI

    图 2  UTBB FDSOI的FBB和RBB背偏

    Figure 2.  Back bias in UTBB FDSOI FBB and RBB

    图 3  环阵电路结构

    Figure 3.  RO circuit structure

    图 4  28 nm体硅CMOS工艺环阵体偏电压对输出频率的影响

    Figure 4.  Output frequency response to body bias voltage of 28 nm bulk CMOS RO

    图 5  22 nm FDSOI工艺环阵背偏电压对输出频率的影响

    Figure 5.  Output frequency response to back bias voltage of 22 nm FDSOI RO

    图 6  28 nm体硅CMOS工艺环阵体偏电压对工作电流的影响

    Figure 6.  Operating current response to body bias voltage of 28 nm bulk CMOS RO

    图 7  22 nm FDSOI工艺环阵背偏电压对工作电流的影响

    Figure 7.  Operating current response to back bias voltage of 22 nm FDSOI RO

    图 8  22 nm FDSOI测试芯片版图

    Figure 8.  22 nm FDSOI test chip layout

    图 9  22 nm FDSOI工艺环阵输出频率仿真和实测对比

    Figure 9.  Comparison of output frequency of 22 nm FDSOI RO between simulation and test

    表  1  2种工艺环阵的输出频率对比

    Table  1.   Comparison of output frequency of RO between two processes

    MHz
    工艺环阵 最小值 正常值 最大值
    28nm体硅CMOS 92.8 120 127
    22nm FDSOI 57.8 158 206
    下载: 导出CSV

    表  2  2种工艺环阵的静态电流对比

    Table  2.   Comparison of standby current of RO between two processes

    A
    工艺环阵 最小值 正常值 最大值
    28 nm体硅CMOS 1.70×10-8 2.34×10-7 1.26×10-6
    22 nm FDSOI 1.33×10-9 2.99×10-9 5.34×10-9
    下载: 导出CSV

    表  3  2种工艺环阵的工作电流对比

    Table  3.   Comparison of operating current of RO between two processes

    A
    工艺环阵 最小值 正常值 最大值
    28nm体硅CMOS 6.78×10-5 1.01×10-4 1.29×10-4
    22nm FDSOI 2.44×10-5 7.03×10-5 9.04×10-5
    下载: 导出CSV

    表  4  22 nm FDSOI工艺环阵输出频率仿真与实测对比

    Table  4.   Comparison of output frequency of 22 nm FDSOI RO between simulation and test

    背偏电压/V 输出频率/MHz
    仿真值 实测值
    (0, 0) 158 154
    (+1, 0) 177 175
    (+1, -1) 201 193
    (+2, 0) 205 195
    (+2, -2) 255 239
    下载: 导出CSV
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出版历程
  • 收稿日期:  2018-03-20
  • 录用日期:  2018-06-08
  • 刊出日期:  2018-11-20

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