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一种新型低功耗SRAM读写辅助电路设计

郭春成 郝旭丹 陈霏

郭春成, 郝旭丹, 陈霏等 . 一种新型低功耗SRAM读写辅助电路设计[J]. 北京航空航天大学学报, 2020, 46(8): 1618-1624. doi: 10.13700/j.bh.1001-5965.2019.0533
引用本文: 郭春成, 郝旭丹, 陈霏等 . 一种新型低功耗SRAM读写辅助电路设计[J]. 北京航空航天大学学报, 2020, 46(8): 1618-1624. doi: 10.13700/j.bh.1001-5965.2019.0533
GUO Chuncheng, HAO Xudan, CHEN Feiet al. Design of a novel read and write assisted circuit in low power SRAM[J]. Journal of Beijing University of Aeronautics and Astronautics, 2020, 46(8): 1618-1624. doi: 10.13700/j.bh.1001-5965.2019.0533(in Chinese)
Citation: GUO Chuncheng, HAO Xudan, CHEN Feiet al. Design of a novel read and write assisted circuit in low power SRAM[J]. Journal of Beijing University of Aeronautics and Astronautics, 2020, 46(8): 1618-1624. doi: 10.13700/j.bh.1001-5965.2019.0533(in Chinese)

一种新型低功耗SRAM读写辅助电路设计

doi: 10.13700/j.bh.1001-5965.2019.0533
基金项目: 

国家自然科学基金 61501323

详细信息
    作者简介:

    郭春成  男, 硕士研究生。主要研究方向:低功耗SRAM设计

    郝旭丹  男, 硕士, 高级工程师。主要研究方向:存储器设计

    陈霏  男, 博士, 副教授。主要研究方向:CMOS太赫兹热探测器机理、关键技术研究及用于无线助听器的低功耗超宽带收发机关键技术

    通讯作者:

    郭春成. E-mail:3013204294@tju.edu.cn

  • 中图分类号: TN47

Design of a novel read and write assisted circuit in low power SRAM

Funds: 

National Natural Science Foundation of China 61501323

More Information
  • 摘要:

    针对低电压下静态随机存储器(SRAM)出现的读写性能损失的问题,设计了一种应用于低功耗SRAM的两步控制(DSC)的字线电压辅助电路技术,可以同时实现读和写辅助的功能,降低SRAM的最小工作电压从而降低功耗。写辅助通过字线开启前段的字线过驱(WLOD)实现,提高写数据速度和写阈值(WM);读辅助通过字线开启后段的字线欠驱(WLUD)实现,降低静态噪声,提高稳定性。通过在28 nm互补金属氧化物半导体(CMOS)工艺下,对256 Kbit SRAM进行前仿和后仿仿真验证,结果表明相比于传统结构,应用DSC字线电压技术的SRAM的最小工作电压降低100 mV,写时间减小10%,静态功耗降低30%,版图面积增大4%。

     

  • 图 1  传统6T存储单元结构

    Figure 1.  Conventional 6T bit-cell structure

    图 2  DSC字线电压技术原理示意图

    Figure 2.  Schematic diagram of DSC word-line voltage technique principle

    图 3  延时时间控制模块结构

    Figure 3.  Structure of delay time control module

    图 4  DSC字线电压技术的波形图

    Figure 4.  Waveform of DSC word-line voltage technique

    图 5  DSC字线电压技术的SRAM结构

    Figure 5.  Structure of SRAM under DSC word-linevoltage technique

    图 6  256 Kbit SRAM版图

    Figure 6.  Layout of 256 Kbit SRAM

    图 7  000次蒙特卡罗仿真测得传统结构和DSC结构2种技术的SNM和WM随归一化电源电压的变化

    Figure 7.  Change of SNM and WM of two kinds of techniques (traditional structure and DSC structure) with normalized supply voltage measured by 1 000 times of Monte Carlo simulation

    图 8  -40℃、0.6 V下传统结构和DSC结构2种技术归一化写时间在不同工艺角的对比

    Figure 8.  Comparison of normalized writing time of two kinds of techniques(traditional structure and DSC structure) at different technological angles under -40℃ and 0.6 V

    图 9  -40℃、0.6 V下传统结构和DSC结构2种技术归一化读时间在不同工艺角的对比

    Figure 9.  Comparison of normalized reading time of two kinds of techniques (traditional structure and DSC structure) at different technological angles under -40℃ and 0.6 V

    图 10  125℃传统结构和DSC结构2种技术归一化静态功耗在各自VMIN和不同工艺角下的对比

    Figure 10.  Comparison of normalized static power of two kinds of techniques(traditional structure and DSC structure) at 125℃ under VMIN and different technological angles

    表  1  DSC字线电压技术与其他低VMIN(< 0.6 V)技术对比

    Table  1.   Comparison of DSC word-line voltage technique with other low VMIN (< 0.6 V) technologies

    技术及参数 文献[15] 文献[12] 文献[13] 本文
    工艺/nm 28 28 28 28
    辅助技术 WLUD+NBL NBL+VDDC DSC
    容量/bit 128 K 256 K 2 M 256 K
    MUX 4 8 4 8
    频率@VMIN/MHz 20 66 30 60
    VMIN/V 0.6 0.58 0.5 0.5
    功耗延迟积(PDP) 1 0.283 0.463 0.280
    质量因数(FoM) 1 7.780 1.613 8.153
    注:所有数据均是在TT工艺角,25℃得到;PDP和FoM按文献[15]归一化得到;PDP=VMIN2/FVMIN (数值越低性能越好);FoM=MUX·FVMIN/(VMIN2·AREA)(数值越高性能越好)。
    下载: 导出CSV
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出版历程
  • 收稿日期:  2019-10-09
  • 录用日期:  2020-02-08
  • 刊出日期:  2020-08-20

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