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芯片间时间触发通信综合规划方法及其优化

汪晶晶 李峭 熊华钢 李二帅

汪晶晶, 李峭, 熊华钢, 等 . 芯片间时间触发通信综合规划方法及其优化[J]. 北京航空航天大学学报, 2020, 46(1): 170-180. doi: 10.13700/j.bh.1001-5965.2019.0136
引用本文: 汪晶晶, 李峭, 熊华钢, 等 . 芯片间时间触发通信综合规划方法及其优化[J]. 北京航空航天大学学报, 2020, 46(1): 170-180. doi: 10.13700/j.bh.1001-5965.2019.0136
WANG Jingjing, LI Qiao, XIONG Huagang, et al. Integrated planning method and optimization for off-chip time-triggered communication[J]. Journal of Beijing University of Aeronautics and Astronautics, 2020, 46(1): 170-180. doi: 10.13700/j.bh.1001-5965.2019.0136(in Chinese)
Citation: WANG Jingjing, LI Qiao, XIONG Huagang, et al. Integrated planning method and optimization for off-chip time-triggered communication[J]. Journal of Beijing University of Aeronautics and Astronautics, 2020, 46(1): 170-180. doi: 10.13700/j.bh.1001-5965.2019.0136(in Chinese)

芯片间时间触发通信综合规划方法及其优化

doi: 10.13700/j.bh.1001-5965.2019.0136
基金项目: 

装备预研基金 61403120404

中国民航大学天津市民用航空器适航与维修重点实验室开放基金 2017SW02

载人航天预先研究项目 060301

详细信息
    作者简介:

    汪晶晶, 女, 硕士研究生。主要研究方向:航空电子系统综合化互连

    李峭, 男, 博士, 讲师, 硕士生导师。主要研究方向:航空电子网络、分布式实时系统

    熊华钢, 男, 博士, 教授, 博士生导师。主要研究方向:航空电子综合、高速数据总线

    通讯作者:

    李峭, E-mail:avionics@buaa.edu.cn

  • 中图分类号: V247;TP393

Integrated planning method and optimization for off-chip time-triggered communication

Funds: 

Equipment Pre-research Fund 61403120404

Civil Aircraft Airworthiness and Maintenance Key Laboratory Fund of Civil Aviation University of China 2017SW02

Manned Space Pre-research Project 060301

More Information
  • 摘要:

    随着片上系统(SoC)的处理能力逐渐接近传统的综合核心处理模块,航空电子系统向着微小型综合化的芯片间系统发展;时间触发交换式互连可以保证芯片间消息传递的严格时间确定性。考虑芯片间互连交换结构轻量化和收发端口有限的特点,在拓扑、路由和调度时刻等网络资源相互制约的条件下,提出了芯片间时间触发通信综合规划方法,即根据时间触发消息集合和芯片端口配置,同时求解得到芯片间网络拓扑结构、消息路由和调度时刻表的规划结果。其中,采用免疫算法整体优化了各条消息在网络资源分配过程中的求解次序。仿真实验表明,与不考虑整体优化的综合规划方法相比,优化后的规划结果在减少拓扑结构中多余路径开销的同时,避免消息传输路径拥堵,降低消息端到端延迟,保证了消息集的可调度性。

     

  • 图 1  芯片间互连拓扑结构示意图

    Figure 1.  Schematic diagram of off-chip interconnection topology structure

    图 2  拓扑更新过程示意图

    Figure 2.  Schematic diagram of topology update process

    图 3  免疫操作示意图

    Figure 3.  Schematic diagram of immune operation

    图 4  开销函数示意图

    Figure 4.  Schematic diagram of cost function

    图 5  不同芯片个数下开销函数值和可调度比例随消息个数变化

    Figure 5.  Cost function values and schedulability rates at different message numbers under various chip numbers

    图 6  不同芯片个数下端到端延迟随消息个数变化

    Figure 6.  End-to-end delay at different message numbers under various chip numbers

    图 7  不同芯片个数下亲和度进化曲线

    Figure 7.  Affinity evolution curves under various chip numbers

    表  1  消息集合示例

    Table  1.   Example of message set

    消息编号 周期/μs 长度/Byte 源节点 目的节点
    1 400 23 1 4
    2 400 683 2 4
    3 100 433 3 4
    4 400 1 429 1 2
    5 100 183 2 4
    6 400 233 1 5
    7 200 483 2 6
    8 50 43 2 1
    9 100 124 5 3
    10 400 345 6 2
    下载: 导出CSV

    表  2  实验组别参数

    Table  2.   Parameters of experimental groups

    消息组别 芯片个数 消息个数 消息长度范围/ Byte 周期范围/μs
    1 6 10~40 23~1 483 50~400
    2 8 10~40 14~1 468 50~400
    3 10 10~40 13~1 454 50~400
    4 12 10~40 11~1 465 50~400
    5 14 10~40 35~1 457 50~400
    下载: 导出CSV

    表  3  优化TRS综合规划方法和增量化SMT方法可调度性对比

    Table  3.   Schedulability comparison between optimized TRS and incremental SMT

    消息组别 增量化SMT方法消息个数 优化TRS综合规划方法消息个数
    10 20 30 40 10 20 30 40
    消息组别1(6芯片个数) × × ×
    消息组别2(8芯片个数) ×
    消息组别3(10芯片个数) ×
    消息组别4(12芯片个数) × ×
    消息组别5(14芯片个数) × ×
    下载: 导出CSV
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出版历程
  • 收稿日期:  2019-04-01
  • 录用日期:  2019-09-03
  • 刊出日期:  2020-01-20

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