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应用于智能芯片的可视化反馈系统研究

李欣致 董胜波 崔向阳 刘志哲 郭广浩

李欣致, 董胜波, 崔向阳, 等 . 应用于智能芯片的可视化反馈系统研究[J]. 北京航空航天大学学报, 2020, 46(8): 1494-1502. doi: 10.13700/j.bh.1001-5965.2019.0518
引用本文: 李欣致, 董胜波, 崔向阳, 等 . 应用于智能芯片的可视化反馈系统研究[J]. 北京航空航天大学学报, 2020, 46(8): 1494-1502. doi: 10.13700/j.bh.1001-5965.2019.0518
LI Xinzhi, DONG Shengbo, CUI Xiangyang, et al. Visual feedback system applied to AI chips[J]. Journal of Beijing University of Aeronautics and Astronautics, 2020, 46(8): 1494-1502. doi: 10.13700/j.bh.1001-5965.2019.0518(in Chinese)
Citation: LI Xinzhi, DONG Shengbo, CUI Xiangyang, et al. Visual feedback system applied to AI chips[J]. Journal of Beijing University of Aeronautics and Astronautics, 2020, 46(8): 1494-1502. doi: 10.13700/j.bh.1001-5965.2019.0518(in Chinese)

应用于智能芯片的可视化反馈系统研究

doi: 10.13700/j.bh.1001-5965.2019.0518
详细信息
    作者简介:

    李欣致  女,博士研究生,工程师。主要研究方向:控制科学与工程

    董胜波  男,博士,研究员,博士生导师。主要研究方向:控制科学与工程

    崔向阳  男,硕士,工程师。主要研究方向:智能信息处理

    刘志哲  男,博士,研究员。主要研究方向:SoC芯片和智能处理器

    郭广浩  男,博士研究生,工程师。主要研究方向:智能芯片处理

    通讯作者:

    董胜波, E-mail:shbdong@aliyun.com

  • 中图分类号: TP183

Visual feedback system applied to AI chips

More Information
  • 摘要:

    当前,市场上普遍使用的负责推理的终端人工智能(AI)芯片使用训练好的参数对数据进行快速高效运算。但在通常训练过程中使用的数据集和真实数据的分布不一致,由此获得的参数会导致终端AI芯片识别准确度降低。为此,提出了一种基于终端AI芯片的可视化反馈系统架构方法。使用反卷积特征可视化方法,在具有高效计算性能的终端AI芯片上,对卷积核参数进行迭代优化,达到可识别该图像目的。相比于CPU/GPU和FPGA,所提架构在卷积神经网络模型里,更具有高效处理能力和灵活可塑性。实验表明,该研究有效提高了终端AI芯片的普适性、识别准确度和处理效率。

     

  • 图 1  反卷积可视化处理流程

    Figure 1.  Deconvolution visualization process flow

    图 2  卷积神经网络结构

    Figure 2.  Convolutional neural network structure

    图 3  AI芯片云端和终端区别

    Figure 3.  Difference between AI chip cloud and terminal

    图 4  算法实现流程图

    Figure 4.  Algorithm implementation flow chart

    图 5  对图像进行快速卷积、激活和池化处理

    Figure 5.  Fast convolution, activation and pooling process of image

    图 6  对图像进行反激活和反卷积处理

    Figure 6.  Deactivate and deconvolve process of image

    图 7  卷积核优化前后反卷积图像和识别结果

    Figure 7.  Deconvolution image and recognition results before and after convolution kernel optimization

    图 8  可视化反馈AI处理器

    Figure 8.  Visual feedback AI processor

    图 9  AI芯片反卷积可视化硬件处理流程

    Figure 9.  AI chip deconvolution visualization hardware processing flow

    图 10  验证平台流程

    Figure 10.  Verification platform process

    表  1  不同模型实验结果对比

    Table  1.   Comparison of experimental results among different models

    模型 优化前识别率/% 优化后识别率/% 平均处理时间/ms 平均优化参数时间/s
    CPU GPU FPGA 本文架构 CPU GPU FPGA 本文架构
    AlexNet 54.71 56.26 1 315.1 26.3 3.87 1.94 75 938.3 1 518.65 371.8 48.88
    ResNet18 65.39 67.12 5 720.2 161.8 12.84 5.26 188 326.9 22 003.5 725.3 122.29
    ResNet50 66.82 67.87 21 736.95 441.8 38.15 14.08 327 688.8 54 300.6 1 964.5 301.73
    ResNet101 67.63 68.03 39 126.51 994.1 67.03 25.6 701 909.4 101 542.1 4 553.7 638.59
    YOLO3 54.95 56.42 169 065.6 4 682.5 289.64 116.28 2 816 060.9 459 684.2 22 003.5 2 701.6
    下载: 导出CSV
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出版历程
  • 收稿日期:  2019-09-24
  • 录用日期:  2020-02-21
  • 刊出日期:  2020-08-20

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