| Citation: | LI Song, ZHAO Yiqiang, YE Maoet al. Optimization method of scan test compression circuit based on EDT[J]. Journal of Beijing University of Aeronautics and Astronautics, 2020, 46(8): 1601-1609. doi: 10.13700/j.bh.1001-5965.2019.0530(in Chinese)
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To realize test patterns compression more efficient in integrated circuit Design for Test (DFT), and reduce test data volume and test time, the S13207, S15850, S38417 and S38584 benchmark circuits were analyzed using Embedded Deterministic Test (EDT) scan test compression scheme. By studying the factors that affect test compression such as test patterns and shift cycles, a scan test compression circuit optimization method was proposed with constant test ports and constant compression ratios. The results show that the benchmark circuits have a good compression effect when the number of test ports was set to 2 and the compression ratio was set to 12, 14, 16 and 24 respectively. Compared with the traditional Automatic Test Pattern Generation (ATPG), stuck-at faults test data volume was reduced by 3.9-6.4 times, and test time was reduced by 3.8-6.2 times; transition faults test data volume was reduced by 4.1-5.4 times, and test time was reduced by 3.8-5.2 times. By changing the number of test ports and compression ratios, this method discusses various factors that affect test compression and gives an optimized scheme for the scan test circuit compression design. It improved the efficiency of the scan compression test. This method was verified in a large-scale circuit, and the result shows that it can be applied to the design of integrated circuit scan test compression.
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