| Citation: | GUO Chuncheng, HAO Xudan, CHEN Feiet al. Design of a novel read and write assisted circuit in low power SRAM[J]. Journal of Beijing University of Aeronautics and Astronautics, 2020, 46(8): 1618-1624. doi: 10.13700/j.bh.1001-5965.2019.0533(in Chinese)
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In order to solve the problem of read and write performance loss in Static Random-Access Memory (SRAM) under low voltage, a novel Dual-Step Control (DSC) word-line voltage technique for low power SRAM is designed, which can simultaneously realize read and write performance and reduce the minimum operation voltage of SRAM. Thus the power consumed is reduced. Write-assist implementation uses the Word-Line Over Drive (WLOD) at the beginning of the word-line to reduce the write access time and improve Write Margin (WM). And read-assist implementation uses the Word-Line Under Drive (WLUD) after the WLOD to reduce static noise and increase the stability. A 256 Kbit SRAM pre-sim and post-sim simulation, which is designed in 28 nanometer Complementary Metal Oxide Semiconductor (CMOS) process, demonstrates that DSC-SRAM lowers the minimum operation voltage by 100 mV, reduces the write access time by 10%, decreases the static power by 30%, and increases its layout area by 4%, compared to the conventional SRAM structure.
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