| Citation: | LI Zongzhe, HE Jiaji, MA Haocheng, et al. A hardware Trojan insertion prevention method based on layout filling with A2-RO circuit[J]. Journal of Beijing University of Aeronautics and Astronautics, 2022, 48(3): 514-521. doi: 10.13700/j.bh.1001-5965.2020.0592(in Chinese)
|
During the chip manufacturing process of integrated circuits, attackers can use blank areas in the circuit layout to implant hardware Trojans. For this reason, this paper proposes a method to prevent inserting hardware Trojans by filling the layout with A2-RO circuit. The goal of protection is reducing the blank areas in the circuit layout. This paper designs the power consumption characterization structure named A2-RO that can dynamically monitor the flipping of rare nodes. And the iterative filling algorithm and the path construction algorithm are proposed. We construct the A2-RO circuit in the blank area intelligently to improve the security level of the circuit. We apply the benchmark circuits in ISCAS'85 and ISCAS'89 as the research object for simulation based on the SMIC 180 nm process. The simulation results show that after filling the layout, the area utilization rate of the chip will be increased to more than 95%, and the remaining blank area cannot be filled with the smallest standard cell. After the removal attack of A2-RO circuit, the change of side channel current is 1.921 mA. The A2-RO circuit can effectively protect the blank areas. The additional routing overhead for layout filling can be controlled within 7%, and the impact on the critical path delay is within 1.2%.
| [1] |
GUIN U, ZHOU Z, SINGH A. Robust design-for-security architecture for enabling trust in IC manufacturing and test[J]. IEEE Transactions on Very Large Scale Integration Systems, 2018, 26(5): 818-830. doi: 10.1109/TVLSI.2018.2797019
|
| [2] |
YASIN M, RAJENDRAN J, SINANOGLU O, et al. On improving the security of logic locking[J]. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2016, 35(9): 1411-1424. doi: 10.1109/TCAD.2015.2511144
|
| [3] |
ZHANG J L, QU G. Recent attacks and defenses on FPGA-based systems[J]. ACM Transactions on Reconfigurable Technology and Systems, 2019, 12(3): 1-25.
|
| [4] |
HOSSEIN-TALAEE H, JAHANIAN A. Layout vulnerability reduction against Trojan insertion using security-aware white space distribution[C]//2017 IEEE Computer Society Annual Symposium on VLSI. Piscataway: IEEE Press, 2017, 1: 551-555.
|
| [5] |
SALMANI H, TEHRANIPOOR M. Vulnerability analysis of a circuit layout to hardware Trojan insertion[J]. IEEE Transactions on Information Forensics and Security, 2016, 11(6): 1214-1225. doi: 10.1109/TIFS.2016.2520910
|
| [6] |
黄钊, 王泉, 杨鹏飞. 硬件木马: 关键问题研究进展及新动向[J]. 计算机学报, 2019, 42(5): 67-91. https://www.cnki.com.cn/Article/CJFDTOTAL-JSJX201905005.htm
HUANG Z, WANG Q, YANG P F. Hardware Trojan: Research progress and new trends on key problems[J]. Chinese Journal of Computers, 2019, 42(5): 67-91(in Chinese). https://www.cnki.com.cn/Article/CJFDTOTAL-JSJX201905005.htm
|
| [7] |
LI H, LIU Q, ZHANG J L. A survey of hardware Trojan threat and defense[J]. Integration, 2016, 55: 426-437. doi: 10.1016/j.vlsi.2016.01.004
|
| [8] |
COCCHI R P, BAUKUS J P, CHOW L W, et al. Circuit camouflage integration for hardware IP protection[C]//2014 51st ACM/EDAC/IEEE Design Automation Conference. Piscataway: IEEE Press, 2014: 1-5.
|
| [9] |
XIAO K, FORTE D, TEHRANIPOOR M. A novel built-in self-authentication technique to prevent inserting hardware Trojans[J]. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2014, 33(12): 1778-1791. doi: 10.1109/TCAD.2014.2356453
|
| [10] |
BA P S, DUPUIS S, PALANICHAMY M, et al. Hardware trust through layout filling: A hardware Trojan prevention technique[C]//2016 IEEE Computer Society Annual Symposium on VLSI. Piscataway: IEEE Press, 2016: 254-259.
|
| [11] |
SUPON T M, SEYEDBARHAGH M, RASHIDZADEH R, et al. Hardware Trojan prevention through limiting access to the active region[C]//14th International Conference on Design & Technology of Integrated Systems in Nanoscale Era. Piscataway: IEEE Press, 2019: 1-6.
|
| [12] |
LIU Y, ZHAO Y, HE J, et al. A statistical test generation based on mutation analysis for improving the hardware Trojan detection[J]. Journal of Circuits, Systems and Computers, 2020, 29(3): 10-25.
|
| [13] |
YANG K, HICKS M, DONG Q, et al. A2: Analog malicious hardware[C]//Security & Privacy. Piscataway: IEEE Press, 2016: 18-37.
|
| [14] |
SAHA S, CHAKRABORTY R S, NUTHAKKI S S, et al. Improved test pattern generation for hardware Trojan detection using genetic algorithm and boolean satisfiability[C]//International Workshop on Cryptographic Hardware and Embedded Systems. Berlin: Springer, 2015: 577-596.
|
| [15] |
赵永嘉, 戴树岭. 基于图像骨架和贪婪算法的无人机航路规划[J]. 北京航空航天大学学报, 2010, 36(4): 474-477. https://bhxb.buaa.edu.cn/CN/Y2010/V36/I4/474
ZHAO Y J, DAI S L. Unmanned aircraft vehicle path planning based on image skeleton and greedy algorithm[J]. Journal of Beijing University of Aeronautics and Astronautics, 2010, 36(4): 474-477(in Chinese). https://bhxb.buaa.edu.cn/CN/Y2010/V36/I4/474
|
| [16] |
李红, 张志宾. 基于快速模拟退火的组合聚类算法[J]. 北京航空航天大学学报, 2019, 45(8): 1646-1652. doi: 10.13700/j.bh.1001-5965.2018.0647
LI H, ZHANG Z B. Ensemble clustering algorithm based on rapid simulated annealing[J]. Journal of Beijing University of Aeronautics and Astronautics, 2019, 45(8): 1646-1652(in Chinese). doi: 10.13700/j.bh.1001-5965.2018.0647
|
Figures(11) / Tables(3)
Copyright © Journal of Beijing University of Aeronautics and Astronautics
Address: Editorial Department of Journal of Beijing University of Aeronautics and Astronautics, 37 Xueyuan Road, Haidian District, Beijing Post Code: 100191 Email: jbuaa@buaa.edu.cn
Supported by:
Beijing Renhe Information Technology Co., Ltd.
DownLoad:
