Citation: | Wang Guang, Shen Xubang. Design of buffer architecture for multi-media stream microprocessor[J]. Journal of Beijing University of Aeronautics and Astronautics, 2006, 32(01): 74-78. (in Chinese) |
[1] Burger, Goodman J R, Kägi A. Memory bandwidth limitations of future microprocessors. In:Proc 23rd Ann Int'l Symp Computer Architecture, Association of Computing Machinery. New York:ACM Press, 1996.79~90 [2] Bakshi A, Gaudiot J L. Memory latency:to tolerate or to reduce. In:Proceedings of the 12th Symposium on Computer Architecture and High Performance Computing. Brazil:Sao Pedro, 2000.24~27 [3] Stanford. Streaming supercomputer. The 2002 Annual Technical Report, Chapter 5,2002 [4] Rixner S. Stream processor architecture[M] Boston:Kluwer Academic Publishers,2001 [5] Seznec A. A case for two-way skewed-associative caches. In:Proceedings of the 20th Annual International Symposium on Computer Architecture. San Diego:CA,1993.169~178 [6] Chen T F, Baer J L. Effective hardware-based data prefetching for high performance multiprocessors[J] IEEE Transactions on Computers,1995,44(5):609~623 [7] Eggers S. Simultaneous multithreading:a platform for next-generation processors[J] IEEE Micro,1997,12~19 [8] Patterson D, Anderson T, Cardwell N, et al. A case for intelligent RAM:IRAM[J] IEEE Micro,1997,17(2) [9] Oskin M, Chong F, Sherwood T. Active pages:a model of computation for intelligent memory. In:Proceedings of the 25th Annual International Symposium on Computer Architecture. Barcelona, 1998.192~203 [10] Rixner S,William J. Memory access scheduling. In:ISCA 2000. 2000. 128~138 [11] Zhou G, Menas Kafatos. Future intelligent earth observing satellites. In:Pecora 15/Land Satellite Information IV/ISPRS Commission I/FIEOS 2002 Conference Proceedings. Hanover:University of Hannover, 2002.1~8 [12] Cloude S, Papathanassiou K, Reigber A, et al. Multi-frequency polarimetric SAR interferometry for vegetation structure extraction. In:Proceedings of IGARSS’ 2000. 2000. 129~131
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