Software bypass and fine-grained parallel scheduling on VLIW

[1] Postiff M A, Greene D A, Tyson G S, et al. The limits of instruction level parallelism in SPEC95 applications[J]. ACM SIGARCH Computer Architecture News, 1999, 27(1):31~34[2] Free Soreware Fundation Inc. GCC info .[3] Hennessy J L, Patterson D A. Computer architecture:a quantitative approach, second edition[M]. San Francisco:Morgan Kaufmann Publishers, 1995[4] Muchnick S S. Advanced compiler design and implementation [M]. San Francisco:Morgan Kaufmann Publishers, 1997[5] Fisher J A. Trace scheduling:a technique for hlobal microcode compaction[J]. IEEE Trans on Computers, 1981, 30(7):478~490[6] Chen Gang. Effective instruction scheduling with limited registers . Boston:The Division of Engineering and Applied Sciences, Havard University, 2001[7] 吴承勇,连瑞琦,张兆庆,等,协作式全局指令调度与寄存器分配[J].计算机学报,2000,23(5):493~499 Wu Chengyong, Lian Ruiqi, Zhang Zhaoqing, et al. Cooperating global instruction scheduling and instant register allocataion[J]. Chinese J Computers, 2000, 23(5):493~499(in Chinese)[8] Hwu W M, Mahlke S A, Chen W Y, et al. The superblock:an effective technique for VLIW and superscalar compilation[J]. The J of Supercomputing, 1993,7(1-2):229~249[9] Mahlke S A, Lin D C, Chen W Y, et al. Effective compiler supoort for predicated execution using the hyperblock[J]. ACM SIGMICRO Newsletter, 1992,23(1-2):45-54[10] Steven J B. Lookahead scheduling[J]. ACM SIGMICRO Newsletter, 1992,23(1-2):256~259