Image Compression ASIC for Satellite Remote Sensing Application

A VLSI architecture for the algorithm of combining re-sampling with multi-mode adaptive quantization was proposed. With low hardware complexity and fast computation rate, the architecture can deal with huge amount of data and match the requirement of VLSI architectures in regularity, modularity, locality. Based on the architecture, ASIC for real-time compression application for high resolution satellite remote sensing imagery was designed and manufactured using FPGA(Field Programmable Gate Arrays). An outstanding feature of the ASIC is that it can process one pixel during each clock cycle. At the clock frequency of 36MHz, a peak processing speed as high as 288Mbits/s of the image compression ASIC can be reached, with a power consumption lower than 1W.