Volume 37 Issue 9
Sep.  2011
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Lü Weimin, Hu Dong, Ma Jinghua, et al. ESD damage simulation of integrated circuits by the consideration on parasitic parameters[J]. Journal of Beijing University of Aeronautics and Astronautics, 2011, 37(9): 1100-1104. (in Chinese)
Citation: Lü Weimin, Hu Dong, Ma Jinghua, et al. ESD damage simulation of integrated circuits by the consideration on parasitic parameters[J]. Journal of Beijing University of Aeronautics and Astronautics, 2011, 37(9): 1100-1104. (in Chinese)

ESD damage simulation of integrated circuits by the consideration on parasitic parameters

  • Received Date: 27 Sep 2010
  • Publish Date: 30 Sep 2011
  • In the traditional electro-static discharge (ESD) damage simulation based on logic circuit, the influence of layout was not taken into account as usual, and there was larger deviation between the results of simulation and the actual damage, so a new simulation method of ESD damage for integrated circuits was presented by the consideration for parasitic parameters extraction in layout. Firstly the specific simulation process in the application was given. Then the models of kinds of parasitic were defined according to empirical parameter extraction method. Lastly the ESD damage simulation for integrated operational amplifier LM741 as case study was carried out. According to zap test, failure location and electrical performance testing, the results showed have much consistency in simulation and experiment, and the validity of the simulation method is finally verified.

     

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