Volume 35 Issue 11
Nov.  2009
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Wang Rui, Jiang Hongxu, Li Boet al. FPGA-based hardware-efficient architecture for variable block-size motion estimation[J]. Journal of Beijing University of Aeronautics and Astronautics, 2009, 35(11): 1339-1343. (in Chinese)
Citation: Wang Rui, Jiang Hongxu, Li Boet al. FPGA-based hardware-efficient architecture for variable block-size motion estimation[J]. Journal of Beijing University of Aeronautics and Astronautics, 2009, 35(11): 1339-1343. (in Chinese)

FPGA-based hardware-efficient architecture for variable block-size motion estimation

  • Received Date: 11 Nov 2008
  • Publish Date: 30 Nov 2009
  • To improve the hardware efficiency of the FPGA-based(field programmable gate array based)architecture for variable block-size motion estimation, a novel architecture was proposed, which was optimized in both area and speed. This architecture introduced RAM-based SAD(sum of absolute differences) accumulators, which had better performance than register-based combiner in both area and speed. To improve the speed of SADs’ comparison and support partial difference eliminating algorithm, the architecture adopted a systolic comparing chain, which substituted for the bus-based comparator used in former designs. Based on Virtex-II family FPGA from Xilinx Inc., the proposed architecture consumed only 2261 slices, with the clock frequency as high as 164MHz. It means that the architecture could process standard-definition format video with 16×16 search window in real-time. Compared with similar designs, the architecture could save the area by 77% and increase the speed by 218%.

     

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