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Volume 35 Issue 10
Oct.  2009
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Journal of Beijing University of Aeronautics and Astronautics  > 2009  >  35(10): 1237-1240.
Liu Rongke, Yu Peng. Efficient architecture design for AVS de-blocking loop filter[J]. Journal of Beijing University of Aeronautics and Astronautics, 2009, 35(10): 1237-1240. (in Chinese)
Citation: Liu Rongke, Yu Peng. Efficient architecture design for AVS de-blocking loop filter[J]. Journal of Beijing University of Aeronautics and Astronautics, 2009, 35(10): 1237-1240. (in Chinese)
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Efficient architecture design for AVS de-blocking loop filter

  • School of Electronics and Information Engineering, Beijing University of Aeronautics and Astronautics, Beijing 100191, China

  • Received Date: 13 Oct 2008
  • Publish Date: 31 Oct 2009
    Abstract
  • In order to meet the requirements in the real time decoding of high definition(HD) video, an efficient very large-scale integration(VLSI) architecture proper for de-blocking loop filter in audio video coding standard(AVS) was presented. The 8×8 blocks were divided into 4×4 blocks for filtering operations. After centralized process of 4×4 block boundaries, data and filtering operations were performed at the same time by improving filtering order. This architecture can increase the efficiency of pipelining and operating data in the SRAM, thereby highly reducing the total clock cycles of filtering process. Experiment results show that only 196 clock cycles are needed to finish filtering a macro-block for de-blocking filter in AVS. The processing speed increases by 50%. When the maximum frequency is 100 MHz, the real time decoding of HD video can be achieved in this architecture.

     

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    • References(1)
  • [1] GB/T 20090.2-2006,信息技术 先进音视频编码 第2部分:视频[S] GB/T 20090.2-2006, Information technology-advanced coding of audio and video-Part2: video[S](in Chinese) [2] Sheng Bin, Gao Wen, Wu Di. A platform-based architecture of loop filter for AVS Int Conf Signal Process Proc. :IEEE Inc,2004: 571-574 [3] 黄中华,支铮.基于FPGA的AVS环路滤波器设计与实现[J].计算机工程,2007,33(6):222-224 Huang Zhonghua, Zhi Zheng. Design and implementation of AVS loop filter based on FPGA[J]. Computer Engineering, 2007,33(6):222-224(in Chinese) [4] Sheng Bin, Gao Wen, Wu Di. An implemented architecture of deblocking filter for H.264/AVC Proc Int Conf Image Process. :IEEE Computer Society, 2004:665-668 [5] Shih Shenyu, Chang Chengru, Lin Younlong. A near optimal deblocking filter for H.264 advanced video coding Design Automation. :IEEE Inc, 2006:170-175 [6] Liu Tsuming, Lee Wenping, Lin Tingan, et al. A memory-efficient deblocking filter for H.264/AVC video coding Circuits and Systems. :ISCAS, 2005:2140-2143 [7] Zheng Guoqing, Yu Lu. An efficient architecture design for deblocking loop filter Picture Coding Symposium. :PCS -Tektronix. Inc, 2004:343-347
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