Ultra-low voltage ultra-low power NMOS bulk-biased mixer

[1] Park C, Han J, Kim H, et al. A 1.8-GHz CMOS power amplifier using a dual-primary transformer with improved efficiency in the low power region [J]. IEEE Transactions on Microwave Theory and Techniques. 2008, 56(4):782-792 [2] Shebaita A, Ismail Y. Multiple threshold voltage design scheme for CMOS tapered buffers [J]. IEEE Transactions on Circuits and Systems II: Express Briefs , 2008, 55(1):21-25 [3] Gu Q, Xu Z, Huang D. A low power V-band CMOS frequency divider with wide locking range and accurate quadrature output phases [J]. IEEE Journal of Solid-State Circuits, 2008, 43(4):991-998 [4] Chu Fangqing, Li Wei, Su Yanfeng, et al. An implementation of a CMOS Down-conversion mixer for GSM1900 receivers [J]. Chinese Journal of Semiconductors, 2006, 27(3):467-472 [5] Kathiresan G,Toumazou C. A low voltage bulk driven downconversion mixer core IEEE Proceedings of the International Symposium on Circuits and Systems. Orlando, Florida: IEEE, 1999: 598-601 [6] Kienmayer C, Tiebout M, Simburger W, et al. A low-power low-voltage NMOS bulk-mixer with 20 GHz bandwidth in 90 nm CMOS Proceedings of the 2004 International Symposium on Circuits and Systems. Vancouver BC, Canada: IEEE, 2004:385-388 [7] 陈邦媛．射频通信电路[M].北京:科学出版社,2004:72 Chen Bangyuan. RF communication circuit[M]. Beijing: Science Press, 2004:72(in Chinese) [8] Khateb A, Biolek D, Novacek K. On the design of low-voltage low-power bulk-driven CMOS current conveyors 29th International Spring Seminar on Electronics Technology. St. Marienthal, Germany:IEEE,2006: 318-321 [9] De Geronimo G, O-Connor P. MOSFET optimization in deep submicron technology for charge amplifiers [J]. IEEE Transactions on Nuclear Science, 2005,52(6): 3223-3232 [10] Marin M, Deen M J, de Murcia M, et al. Effects of body biasing on the low frequency noise of MOSFETs from a 130 nm CMOS technology Circuits IEE Proceedings Circuits, Devices & Systems. Stevenage: IET Michael Faraday House,2004, 151:95-101 [11] Kyechong Kim, Iliadis A A. Characterization of latch-up in CMOS inverters in pulsed electromagnetic interference environments 2007 International Semiconductor Device Research Symposium. 2007:1-2