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Volume 34 Issue 10
Oct.  2008
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Journal of Beijing University of Aeronautics and Astronautics  > 2008  >  34(10): 1177-1181.
Zhu Di, Shen Gongxun. 2-D parallel memory architecture for video processor[J]. Journal of Beijing University of Aeronautics and Astronautics, 2008, 34(10): 1177-1181. (in Chinese)
Citation: Zhu Di, Shen Gongxun. 2-D parallel memory architecture for video processor[J]. Journal of Beijing University of Aeronautics and Astronautics, 2008, 34(10): 1177-1181. (in Chinese)
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2-D parallel memory architecture for video processor

  • School of Astronautics, Beijing University of Aeronautics and Astronautics, Beijing 100191, China

  • Received Date: 12 Nov 2007
  • Publish Date: 31 Oct 2008
    Abstract
  • Video codec has a very high computation complexity and features intensive vector accesses to memory. A 2-D parallel memory scheme based on linear skewing scheme was proposed. The memory scheme can be combined with simple instruction multiple data (SIMD) vector processor to address the computation challenge of video. The address generation logic and scheme-s micro architecture were analyzed. The scheme uses a data rotation unit to permute data element to form a vector. This method simplified data permutation network which is the bottleneck of most parallel memory schemes. The performance difference between parallel memory and traditional memory were also compared. The kernel module of H.264/AVC such as motion estimation, de-blocking filter and interpolation were investigated based on the proposed memory scheme.

     

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  • [1] Analog Devices Inc. ADSP-BF533 Blackfin processor hrdware reference . Norwood, MA: ADI, 2004 . [2] CEVA Inc. ceva portable multimedia whitepaper . San Jose: CEVA Inc, 2007 . [3] ISO/IEC 14496-10, Advanced video coding for generic audiovisual services[S][4] Tanskanen J K, Sihvo T, Niittylahti J. Byte and modulo addressable parallel memory architecture for video coding [J]. IEEE Transactions on Circuits and Systems for Video Technology, 2004,14(11):1270-1276[5] Park J W. An efficient buffer memory system for subarray access [J]. IEEE Transactions on Parallel and Distributed Systems, 2001, 12(3):316-335[6] Kant S, Mithun U, Pssbk G. Real time H.264 video encoder implementation on a programmable DSP processor for videophone applications // IEEE Consumer Electronics . ICCE -06 Digest of Technical Papers. Las Vegas: IEEE Consumer Electronics, 2006:93-94
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