Design and implementation of multi-rate quasi-cyclic low-density parity-check code decoder

To meet the requirement of using multi-rate low density parity check(LDPC) codes in the communication system, a 7Kbit code length multi-rate LDPC codes decoder architecture was presented and implemented on a Altera field-programmable gate array device. The similarity between different check matrixes of different rate was analyzed and the variable node processing unit (VNU), the check node processing unit (CNU) and the iteration storage location duplication in the decoder were explained. By adding several switches in the input ports of the VNUs and the CNUs, these processing units can work under different code rates. Using pin selection, three operating modes, namely, the irregular 0.4 code mode, the irregular 0.6 code mode and the irregular 0.8 code mode, are supported. The synthesis result indicates that the proposed multi-rate LDPC code decoder using just a little more resources than a single 0.8 rate LDPC code decoder without any performance loss.