Link scheduler for network-on-chip

[1] Benini L, Micheli G D. Networks on chips: a new SoC paradigm[J]. IEEE Computers, 2002, 35(1): 70-78[2] Hu J, Marculescu R. Application-specific buffer space allocation for networks-on-chip router design Proceedings of IEEE/ACM International Conference on Computer-Aided Design. Washington, DC: IEEE CS, 2004: 354-361[3] Sethu H, Shi H, Kanhere S S, et al. A round-robin scheduling strategy for reduced delays in wormhole switches with virtual lanes Proceedings of the International Conference on Communications in Computing. Las Vegas:, 2000:275-278[4] Pirvu M, Bhuyan L, Ni N. The impact of link arbitration on switch performance Proceedings of 5^th International Symposium on High-Performance Computer Architecture. Washington, DC: IEEE CS, 1999: 228-235[5] Galles M. Spider: a high-speed network interconnect[J]. IEEE Micro, 1997, 17(1): 34-39[6] Stunkel C B, Shea D G, Aball B, et al. The SP2 high-performance switch[J]. IBM Systems Journal, 1995, 34(2): 185-204[7] Nielsen K H. Evaluation of real-time performance models in wormhole-routed on-chip networks. [8] Kavaldjiev N, Smit G J M. An energy-efficient network-on-chip for a heterogeneous tiled reconfigurable systems-on-chip Proceedings of Digital System Design, EUROMICRO Systems on (DSD’04). Washington, DC: IEEE CS, 2004: 492-498[9] Pande P P, Grecu C, Ivanov A, et al. High-throughput switch-based interconnect for future SoCs Proceedings of 3rd IEEE International Workshop on System-on-Chip for Real-Time Applications. Washington, DC: IEEE CS, 2003: 304-310[10] Scott S L, Thorson G M. The cray T3E network: adaptive routing in a high performance 3D torus Proceedings of Hot Interconnects IV. Stanford,CA: Stanford University, 1996: 147-156[11] Dally J, Seitz C L. Deadlock-free message routing in multiprocessor interconnection networks[J]. IEEE Transactions on Computers, 1987, 36(5): 547-553[12] 尹宝林,何自强,许光汉,等.离散数学[M].北京:高等教育出版社, 1998 Yin Baolin, He Ziqiang, Xu Guanghan, et al. Discrete mathematics[M]. Beijing: Higer Education Press, 1998(in Chinese)[13] Jerraya A A, Tenhunen H, Wolf W. Guest editors- introduction: multiprocessor systems-on-chips[J]. IEEE Computer, 2005, 38(7): 36-40[14] Chien A A. A cost and speed model for k-ary n-cube wormhole routers[J]. IEEE Transactions on Parallel and Distributed Systems, 1998,9(2): 150-162