基于多策略融合蚁狮优化算法的MPRM逻辑电路面积优化方法

潘家义; 何振学; 赵晓君; 何俊才; 周宇豪; 王翔

doi:10.13700/j.bh.1001-5965.2024.0259

基于多策略融合蚁狮优化算法的MPRM逻辑电路面积优化方法

doi: 10.13700/j.bh.1001-5965.2024.0259

潘家义^{1, 2},
何振学^{1, 2, ,},
赵晓君^{1, 2},
何俊才^{1, 2},
周宇豪³,
王翔⁴

1.
河北农业大学智能农业装备研究院，保定 071001
2.
河北农业大学河北省农业大数据重点实验室，保定 071001
3.
同济大学软件学院，上海 201804
4.
北京航空航天大学电子信息工程学院，北京 100191

基金项目:

国家自然科学基金(62102130)；中央引导地方科技发展资金项目(226Z0201G)；河北省自然科学基金(F2024204001,F2020204003)；河北省青年拔尖人才计划项目(BJ2019008)；河北省高等学校科学技术研究项目(QN2024138)；河北省省属高等学校基本科研业务费研究项目(KY2022073)

详细信息

通讯作者:
E-mail：hezhenxue@buaa.edu.cn

中图分类号: V443；TP391.72
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- 被引次数: 0
出版历程
- 收稿日期: 2024-04-26
- 录用日期: 2024-06-14
- 网络出版日期: 2024-07-08
- 整期出版日期: 2026-06-30

Area optimization approach for MPRM logic circuits based on multi-strategy synergy ant lion optimization algorithm

PAN Jiayi^{1, 2},
HE Zhenxue^{1, 2
, ,},
ZHAO Xiaojun^{1, 2},
HE Juncai^{1, 2},
ZHOU Yuhao³,
WANG Xiang⁴

1.
Intelligent Agricultural Equipment Research Institute，Hebei Agriculture University，Baoding 071001，China
2.
Key Laboratory of Agricultural Big Data of Hebei Province，Hebei Agriculture University，Baoding 071001，China
3.
School of Software Engineering，Tongji University，Shanghai 201804，China
4.
School of Electronic Information Engineering，Beihang University，Beijing 100191，China

Funds:

National Natural Science Foundation of China (62102130); Central Government Guides Local Science and Technology Development Fund Project (226Z0201G); Natural Science Foundation of Hebei Province (F2024204001,F2020204003); Hebei Youth Talents Support Project (BJ2019008); Science and Technology Research Projects of Higher Education Institutions in Hebei Province (QN2024138); Basic Scientific Research Funds Research Project of Hebei Provincial Colleges and Universities (KY2022073)

More Information

Corresponding author: E-mail：hezhenxue@buaa.edu.cn

摘要

摘要:
针对现有混合极性Reed-Muller (MPRM)逻辑电路面积优化方法优化效果较差的问题，提出一种多策略融合蚁狮优化(MSALO)算法。为解决蚁狮优化(ALO)算法全局搜索能力较差的问题，在算法随机游走阶段应用双策略随机游走机制；为解决算法寻优能力差的问题，针对精英蚁狮个体应用突围机制；为加快算法的收敛速度，引入基于正弦函数的自适应蚂蚁位置更新策略。提出一种基于MSALO算法的MPRM逻辑电路面积优化方法，基于北卡罗莱纳州微电子中心(MCNC)基准测试电路的实验结果表明：基于MSALO算法的MPRM逻辑电路面积优化方法平均面积节省率可在现有优秀群智能优化算法的基础上平均提高27.96%。
- 混合极性Reed-Muller /
- 组合优化问题 /
- 群智能优化 /
- 蚁狮优化 /
- 突围机制
Abstract:
In this paper, we propose a multi-strategy synergy ant lion optimization (MSALO) algorithm to address the problems of insufficient optimization efficacy of existing mixed polarity Reed-Muller (MPRM) circuit area optimization methods. A two-strategy random tour mechanism is used in the algorithm’s random tour stage to address the issue of the ant lion optimization (ALO) algorithm’s poor global search ability. A breakout mechanism is used for elite ant lion individuals to address the issue of poor local exploration ability. To expedite the convergence rate of the algorithm, an adaptive ant position update strategy based on the sine function is introduced. The MPRM circuit area optimization approach based on MSALO is proposed to search for the best polarity corresponding to the MPRM logic circuit with the smallest circuit area by using MSALO. The experimental results based on the Microelectronics Center of North Carolina (MCNC) benchmark test circuit demonstrate that the average area savings rate of the area optimization strategy based on MSALO may be increased by an average of 27.96% when compared to the current state-of-the-art swarm intelligence optimization algorithms.
- mixed polarity Reed-Muller /
- combinatorial optimization problem /
- swarm intelligent optimization /
- ant lion optimization /
- breakout mechanism

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图 1 突围机制示意图

Figure 1. Schematic diagram of the breakout mechanism

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图 2 编码与解码流程

Figure 2. Encoding and decoding flowchart

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图 3 本文方法流程

Figure 3. Flowchart of the proposed method

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图 4 amd电路收敛曲线

Figure 4. Circuit convergence curves of amd

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图 5 br1电路收敛曲线

Figure 5. Circuit convergence curves of br1

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图 6 clip电路收敛曲线

Figure 6. Circuit convergence curves of clip

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图 7 newtpla电路收敛曲线

Figure 7. Circuit convergence curves of newtpla

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图 8 pdc电路收敛曲线

Figure 8. Circuit convergence curves of pdc

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图 9 t3电路收敛曲线

Figure 9. Circuit convergence curves of t3

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表 1 4种算法的逻辑电路面积优化对比实验数据

Table 1. Comparison experimental data of logic circuit area optimization of four algorithms

电路名称	算法运行10次逻辑电路面积最优值				算法运行10次逻辑电路面积平均值				S₁/%	S₂/%	S₃/%
电路名称	MSALO	ALO	ChOA	SAO	MSALO	ALO	ChOA	SAO	S₁/%	S₂/%	S₃/%
5xp1	37	37	37	37	37	39.7	37.4	40.8	6.80	1.07	9.31
exps	51	53	51	65	51	64.6	52.2	89.2	21.05	2.30	42.83
clip	260	260	260	260	264	265.7	268.8	271.1	0.64	17.86	2.62
br1	126	126	126	137	126	145.6	140.6	146.7	13.46	10.38	14.11
t3	113	129	123	161	119.2	155.4	139.6	176.6	23.29	14.61	32.50
alu1	7	7	7	8	7	7.4	7.1	12.2	5.41	1.41	42.62
misex3	933	1876	1377	2484	933	2469.6	1892.2	3124.8	62.22	50.69	70.14
table3	1528	2042	1891	2042	1528	2326.9	2192.2	2584.7	34.33	30.30	40.88
amd	309	375	346	383	323.1	415.7	374	439	22.28	13.61	26.40
gary	577	726	650	708	593.2	816.7	731.8	876.9	27.37	18.94	32.35
newtpla	35	44	47	59	35	66.5	63.4	82.1	47.37	44.79	57.37
pdc	185	185	185	230	185	259.4	252.3	297.9	28.68	26.67	37.90
table5	50	92	92	76	52.8	114	110.3	105	53.68	52.13	49.71
注：S₁、S₂、S₃分别为MSALO算法与ALO、ChOA、SAO算法相比的平均面积节省率。

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