基于GPU的LDPC存储优化并行译码结构设计

葛帅; 刘荣科; 侯毅

基于GPU的LDPC存储优化并行译码结构设计

北京航空航天大学电子信息工程学院, 北京 100191

基金项目: 航空电子系统综合技术重点实验室和航空科学基金联合资助项目(20115551022)

详细信息

作者简介:
葛帅(1988-),男,黑龙江哈尔滨人,硕士生,gysn.erwrew@gmail.com.

中图分类号: TN911.2
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- 被引次数: 0
出版历程
- 收稿日期: 2012-04-18
- 网络出版日期: 2013-03-31

Memory optimized parallel LDPC decoder architecture design on GPU

School of Electronic and Information Engineering, Beijing University of Aeronautics and Astronautics, Beijing 100191, China

摘要

摘要: 提出了一种基于Nvidia公司Fermi架构图形处理单元(GPU,Graphic Processing Unit)的分层低密度奇偶校验LDPC(Low-Density Parity-Check)码译码算法的译码器结构优化设计.利用GPU架构的并行性特点,采用帧间与层内双重并行的处理方式,充分利用流多处理器硬件资源,有效缓解了分层译码算法并行度受限的问题.此外,通过采取片上constant memory存储器压缩存储校验矩阵以及利用片外global memory存储器对译码迭代信息进行联合访问的优化方法,有效降低了访存延迟,提高了译码吞吐率.测试结果表明,通过采用多帧并行处理和存储器访问优化可以提升基于GPU的LDPC译码器吞吐率14.9～34.8倍.
- 准循环低密度奇偶校验码 /
- 图形处理单元 /
- 多帧处理 /
- 分层译码算法 /
- 存储优化
Abstract: An optimized decoding architecture was proposed for low-density parity-check (LDPC) codes layered decoding algorithm based on Nvidia's Fermi graphic processing unit (GPU). In accordance with the parallelism characteristics in GPU hardware structure, inter-frame and intra-layer parallelization processing were adopted to fully utilize the resource of streaming multiprocessors (SM) and mitigate the decoding parallelism limitation in layered decoding algorithm. Secondly, by compressed storing parity-check matrix in on-chip constant memory and coalescing access the exchange information in off-chip global memory, the memory access latency was reduced, and hence the decoding throughput was improved. Simulation results show that 14.9x to 34.8x speed-up for decoding throughput is obtained by using multi-frame processing and memory access optimization on GPU platform.
- quasi-cyclic low-density parity-check (QC-LDPC) codes /
- graphic processing unit (GPU) /
- multi-frame processing /
- layered decoding algorithm /
- memory access optimization

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参考文献(1)

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