FPGA-based hardware-efficient architecture for variable block-size motion estimation
-
摘要: 针对可变尺寸块运动估计(VBSME,Variable Block-Size Motion Estimation)的硬件结构在现场可编程门阵列(FPGA, Field Programmable Gate Array)上实现时消耗资源多且速度慢的问题,提出了一种面积和速度优化的VBSME硬件结构.其中,绝对差累加和(SAD,Sum of Absolute Differences)的计算采用基于随机存储器(RAM,Random Access Memory)的累加计算方式,比基于寄存器合并的方式节省了面积并增加了速度;通过采用脉动比较链而非总线结构,增强了多个SAD值的比较能力,并能高效地实现对部分差排除算法(PDE,Partial Difference Elimination)的支持.基于Virtex-II型FPGA器件,本结构消耗了2261个slice,时钟频率达到164MHz,在搜索窗口为16×16时可实时处理标清格式的视频.与同类设计相比,设计的面积可减少77%,速度增加218%,FPGA的硬件效率显著提升.Abstract: To improve the hardware efficiency of the FPGA-based(field programmable gate array based)architecture for variable block-size motion estimation, a novel architecture was proposed, which was optimized in both area and speed. This architecture introduced RAM-based SAD(sum of absolute differences) accumulators, which had better performance than register-based combiner in both area and speed. To improve the speed of SADs’ comparison and support partial difference eliminating algorithm, the architecture adopted a systolic comparing chain, which substituted for the bus-based comparator used in former designs. Based on Virtex-II family FPGA from Xilinx Inc., the proposed architecture consumed only 2261 slices, with the clock frequency as high as 164MHz. It means that the architecture could process standard-definition format video with 16×16 search window in real-time. Compared with similar designs, the architecture could save the area by 77% and increase the speed by 218%.
-
[1] ISO/IEC 144962-10, Information technology coding of audio-visual objects part 10: advanced video coding [S] [2] Chen Chingyeh,Chien Shaoyi,Huang Yuwen, et al. Analysis and architecture design of variable block-size motion estimation for H.264/AVC[J].IEEE Trans Circuits Syst,2006,53(3):578-593 [3] Li Brian M H, Leong Philip H W.FPGA-based MSB-first bit-serial variable block size motion estimation processor 2006 IEEE International Conference on Field Programmable Technology. Piscataway,NJ:IEEE Inc,2006:165-172 [4] Yap Swee Yeow, McCanny John V. A VLSI architecture for variable block size video motion estimation[J]. IEEE Trans Circuits Syst Video Technol,2004,51(7):384-389 [5] Sebastin Lpez, Félix Tobajas, Arturo Villar, et al. Low cost efficient architecture for H.264 motion estimation 2005 IEEE International Symposium on Circuits and Systems. Piscataway,NJ: IEEE Inc, 2005: 412-415 [6] Jehng Yeushen, Chen Lianggee, Chiueh Tzidar. An efficient and simple VLSI tree architecture for motion estimation algorithms[J]. IEEE Transactions on Signal Processing,1993,41(2):889-900 [7] Yang Kunmin, Sun Mingting, Wu Lancelot. A family of VLSI designs for the motion compensation block matching algorithm[J].IEEE Transactions on Circuits System,1989,36(10):1317-1325 [8] Kim Jongnam, Choi Taesun. A fast motion estimation for software based real-time video coding[J]. IEEE Transactions on Consumer Electronics, 1999, 45(2): 417-426 [9] Xilinx products table . Xilinx Inc, 2007 . http://www.xilinx.com/ products/tables/fpga.htm [10] Jain Jaswant, Jain Anil. Displacement measurement and its application in interframe image coding[J].IEEE Transactions on Communications,1981,29(12):1799-1808 [11] Tuan Jenchieh, Chang Tiansheuan, Jen Cheinwei. On the data reuse and memory bandwidth analysis for full search block matching VLSI architecture[J]. IEEE Tran Circuits Syst for Video Technol,2002,12(1):61-72 -
点击查看大图
计量
- 文章访问数: 3039
- HTML全文浏览量: 153
- PDF下载量: 1077
- 被引次数: 0
下载:
