Acceleration scheme of RXD algorithm based on FPGA for hyperspectral anomaly target detection
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摘要:
高光谱图像在带来丰富光谱信息的同时，其数据量大和维数高的特性也使得各种目标检测算法进行处理时往往产生庞大的运算量，所以采用可以实现高光谱异常目标检测算法的高速处理方案显得尤为迫切和重要。考虑到现场可编程门阵列（FPGA）强大的并行计算能力和极具灵活的设计方式，针对高光谱异常目标检测RXD算法中协方差矩阵及其逆的计算量过大的问题，以分块并行和正交三角（QR）分解为主要加速思想，利用高层次综合（HLS）工具对算法进行优化，提出了RXD算法在FPGA平台上的加速方案。实验结果表明，所提出的基于FPGA平台的加速方案可以在保持算法检测性能的同时达到相较于CPU实现7.04倍的加速，验证了加速方案的正确有效性。
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关键词:
- 高光谱异常目标检测 /
- RXD算法 /
- 分块并行 /
- 正交三角(QR)分解 /
- 高层次综合(HLS) /
- 加速方案
Abstract:Hyperspectral images bring abundant spectral information, but their large size and high dimensionality also lead to huge calculation. Therefore, it is particularly urgent to develop a high-speed processing scheme for anomaly target detection algorithms. Considering that the field programmable gate arrays (FPGA) are of powerful parallel capability and highly flexible design, aiming at the problem that the computation of the covariance matrix and its inverse is too large in the Reed-Xiaoli Detector (RXD) algorithm, we propose an acceleration scheme of block parallel and QR decomposition for the RXD algorithm based on the FPGA platform, which is optimized by high level synthesis (HLS). Experimental results show that the processing speed of FPGA-based acceleration scheme proposed in this paper is 7.04 times faster than that of CPU-based implementations with the detection performance preserved simultaneously, which verifies that the proposed acceleration scheme is correct and effective.
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图 1 分块相乘求自相关矩阵的描述
Figure 1. Description of finding autocorrelation matrix by block multiplication
图 4 QR分解求逆矩阵的实现方案
Figure 4. Implementation scheme of finding inverse matrix by QR decomposition
图 10 HLS与MATLAB实现结果对比
Figure 10. Comparison of implementation results between HLS and MATLAB
图 11 HLS与MATLAB实现结果的相对误差
Figure 11. Relative error of implementation results of HLS and MATLAB
表 1 添加约束项后2种方法的时序
Table 1. Timing sequence after adding constraints of two methods
方法 最小时延/
clk最大时延/
clk最小数据间隔/clk 最大数据间隔/clk 传统法 4286520030 4286520030 4286520031 4286520031 加速法 733332624 733332624 733332625 733332625 注：clk—一个时钟周期。 
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表 2 加速法的资源利用情况
Table 2. Resource utilization results of acceleration scheme
资源利用数 BRAM_18K DSP48E FF LUT 表达式资源数 0 74 实例资源数 131 11472 27045 存储资源数 40 0 0 乘法器资源数 1747 寄存器资源数 203 总计 40 131 11675 28866 可用资源数 2060 2800 607200 303600 资源利用率/% 1 4 1 9
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表 3 2种方案的时序情况对比
Table 3. Comparison of timing sequence between two schemes
方案 最小时延/
clk最大时延/
clk最小数据间隔/clk 最大数据间隔/clk ① 169502204 354001169 169502205 354001170 ② 57877695 256307850 57877696 256307851
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表 4 添加优化前后2种方案的资源利用情况
Table 4. Comparison of resource utilization results before and after optimization between two schemes
资源利用数 BRAM_18K DSP48E FF LUT 实例资源数 512/288 94/88 14 512/21238 20691/61334 存储资源数 768/432 0 0 乘法器资源数 58/418 寄存器资源数 9/9 总计 1280/720 94/88 14521/21247 20749/61752 可用资源数 2060 2800 607200 303600 资源利用率/% 62/34 3/3 2/3 6/20
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表 5 基于FPGA的RXD算法实现的时序估计结果
Table 5. Timing sequence estimation results for FPGA-based implementation of RXD algorithn
时钟周期/ns 最小时延/
clk最大时延/
clk最小数据间隔/clk 最大数据间隔/clk 9.78 1552545313 1779318286 1552545314 1779318287
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表 6 基于FPGA的RXD算法实现的资源利用情况
Table 6. Resource utilization results for FPGA-based implementation of RXD algorithn
资源利用数 BRAM_18K DSP48E FF LUT 表达式资源数 1 0 5390 实例资源数 40 244 66088 92578 存储资源数 978 0 0 乘法器资源数 10556 寄存器资源数 4109 32 总计 1018 246 70197 108556 可用资源数 2060 2800 607200 303600 资源利用率/% 49 8 11 35
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表 7 CPU和FPGA平台实现RXD算法的处理时间对比
Table 7. Comparison of processing time measured for RXD algorithm between CPU and FPGA implementations
CPU
处理时间/sFPGA 加速比 时钟周期/
ns最小时延/
clk处理时间/s 111.29 9.78 1552545313 15.81 7.04
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