一种混合粒度奇偶校验故障注入检测方法

王沛晶; 刘强

doi:10.13700/j.bh.1001-5965.2018.0464

一种混合粒度奇偶校验故障注入检测方法

doi: 10.13700/j.bh.1001-5965.2018.0464

王沛晶^{1, 2},
刘强^{1, 2, ,}

1.
天津大学微电子学院, 天津 300072
2.
天津市成像与感知微电子技术重点实验室, 天津 300072

基金项目:

国家自然科学基金 61574099

详细信息

作者简介:
王沛晶女, 硕士研究生。主要研究方向:集成电路安全

刘强男, 博士, 副教授, 博士生导师。主要研究方向:大规模集成电路设计与安全

通讯作者:
刘强, E-mail: qiangliu@tju.edu.cn

中图分类号: TN407
计量
- 文章访问数: 632
- HTML全文浏览量: 133
- PDF下载量: 441
- 被引次数: 0
出版历程
- 收稿日期: 2018-08-03
- 录用日期: 2018-09-14
- 网络出版日期: 2019-04-20

Mixed-grain parity-code-based fault detection method against fault injection

WANG Peijing^{1, 2},
LIU Qiang^{1, 2
, ,}

1.
School of Microelectronics, Tianjin University, Tianjin 300072, China
2.
Tianjin Key Laboratory of Imaging and Sensing Microelectronic Technology, Tianjin 300072, China

Funds:

National Natural Science Foundation of China 61574099

More Information

Corresponding author: LIU Qiang, E-mail: qiangliu@tju.edu.cn

摘要

摘要:
为了实现高效的抗故障注入攻击，提出了一种混合粒度奇偶校验故障注入检测方法。传统奇偶校验检测方法为每n比特设置一个奇偶位，表示该n比特的奇偶性。随着n的减小，奇偶位个数增加，资源消耗增加，检测率提高。为了实现故障检测率和资源消耗的折中，对电路故障注入敏感部分或关键部分处理的数据采用细粒度奇偶校验（即n值较小），对其他部分采用粗粒度奇偶校验。以RC5加密算法为例，阐述了混合粒度奇偶校验故障检测方法的原理和应用，并对不同粒度奇偶校验方法的故障检测率及资源使用进行了理论分析。实验结果表明，与整个RC5电路都采用字（n=32 bit）奇偶校验相比，混合粒度奇偶校验故障注入检测方法可以提高故障检测率29.44%，仅增加资源消耗2.48%。
- 奇偶校验 /
- 混合粒度故障检测 /
- 故障检测率 /
- 故障注入攻击 /
- 现场可编程门阵列(FPGA)
Abstract:
For efficient countermeasure against fault injection attacks, a mixed-grain parity-code-based fault detection approach was proposed. Traditional parity-code-based fault detection approach assigns a parity bit per n bits, representing the parity of the n-bit word. As n decreases, the number of parity bits increases, leading to increased resource usage and fault detection rate. To achieve tradeoff between fault coverage and resource usage, the fine-grain parity code (small n) was applied to the data processed in the fault-sensitive parts or critical parts of circuits, and the coarse-grain parity code was applied to other parts of circuits. The approach was applied to RC5 encryption algorithm to explain the principle and application of the mixed-grain parity-code-based fault detection technology, and to theoretically analyze the fault coverage and resource usage of different grain solutions. The experimental results show that, compared to the RC5 circuit with one parity bit per 32 bit, the mixed-grain parity-code-based detection approach improves the fault coverage by 29.44% and increases resource usage slightly by 2.48%.
- parity code /
- mixed-grain fault detection /
- fault coverage /
- fault injection attack /
- field programmable gate array (FPGA)

HTML全文

图 1 奇偶校验故障检测结构

Figure 1. Parity-code-based fault detection architecture

下载: 全尺寸图片幻灯片

图 2 RC5加密电路混合粒度故障检测实现

Figure 2. Architecture of mixed-grain fault detection for RC5 encrypted circuit

下载: 全尺寸图片幻灯片

图 3 时钟故障注入示意图

Figure 3. Schematic diagram of clock fault injection

下载: 全尺寸图片幻灯片

图 4 不同混合粒度检测方法寄存器消耗值

Figure 4. Register utilization of different mixed-grain detection methods

下载: 全尺寸图片幻灯片

图 5 不同混合粒度检测方法故障检测率

Figure 5. Fault coverage of different mixed-grain detection methods

下载: 全尺寸图片幻灯片

表 1 不同粒度校验方法故障检测率理论值

Table 1. Fault coverage in theory of multi-granularity detection methods

不同比特奇偶校验/bit 故障检测率/%

32 50

16 75

8 93.75

4 99.60

下载: 导出CSV

表 2 不同粒度校验方法寄存器消耗理论值

Table 2. Register utilization in theory of multi-granularity detection methods

不同比特奇偶校验/bit 寄存器数量

预测电路比较电路

32 8 1

16 16 2

8 32 4

4 64 8

下载: 导出CSV

表 3 不同粒度校验方法故障检测率实际值

Table 3. Fault coverage in practice of multi-granularity detection methods

不同比特奇偶校验/bit 故障检测率/%

32 51.92

16 73.97

8 89.24

4 96.28

下载: 导出CSV

参考文献(16)

[1]	BARENGHI A, BREVEGLIERI L, KOREN I, et al.Fault injection attacks on cryptographic devices:Theory, practice, and countermeasures[J].Proceedings of the IEEE, 2012, 100(11):3056-3076. doi: 10.1109/JPROC.2012.2188769
[2]	LIU Y N, ZHANG J, WEI L X, et al.DERA: Yet another differential fault attack on cryptographic devices based on error rate analysis[C]//52nd ACM/EDAC/IEEE Design Automation Conference.Piscataway, NJ: IEEE Press, 2015.
[3]	DUTERTRE J M, FOURNIER J J A, MIRBAHA A P, et al.Review of fault injection mechanisms and consequences on countermeasures design[C]//International Conference on Design & Technology of Integrated Systems in Nanoscale Era. Piscataway, NJ: IEEE Press, 2011: 5941421.
[4]	CHU J, BENAISSA M.Error detecting AES using polynomial residue number systems[J].Microprocessors & Microsystems, 2013, 37(2):228-234. http://d.old.wanfangdata.com.cn/NSTLQK/NSTL_QKJJ0229919991/
[5]	SONDON S, MANDOLESI P, JULIAN P, et al.Heavy-ion micro-beam use for transient fault injection in VLSI circuits[C]//International Conference on Plasma Sciences. Piscataway, NJ: IEEE Press, 2014: 7012614.
[6]	KOOLI M, NATALE G D.A survey on simulation-based fault injection tools for complex systems[C]//IEEE International Conference on Design & Technology of Integrated Systems in Nanoscale Era. Piscataway, NJ: IEEE Press, 2014: 6850649.
[7]	BENEVENUTI F, KASTENSMIDT F L.Evaluation of fault attack detection on SRAM-based FPGAs[C]//Test Symposium. Piscataway, NJ: IEEE Press, 2017: 7906747.
[8]	MESTIRI H, BENHADJYOUSSEF N, MACHHOUT M, et al.A robust fault detection scheme for the advanced encryption standard[J].International Journal of Computer Network & Information Security, 2013, 5(6):49-55. http://d.old.wanfangdata.com.cn/OAPaper/oai_doaj-articles_0af74b6851168d87ca2f53435704f022
[9]	TOMASHEVICH V, SRINIVASAN S, FOERG F, et al.Cross-level protection of circuits against faults and malicious attacks[C]//International on-Line Testing Symposium. Piscataway, NJ: IEEE Press, 2012: 150-155.
[10]	MOZAFFARI-KERMANI M, REYHANI-MASOLEH A. Concurrent structure-independent fault detection schemes for the advanced encryption standard[J].IEEE Transactions on Computers, 2010, 59(5):608-622. doi: 10.1109/TC.2010.33
[11]	BERTONI G, BREVEGLIERI L, KOREN I, et al.Concurrent fault detection in a hardware implementation of the RC5 encryption algorithm[J].Application-Specific Systems, Architectures, and Processors, 2003, 16(3):423-432. http://www.wanfangdata.com.cn/details/detail.do?_type=perio&id=CC026508925
[12]	BEDOUI M, MESTIRI H, BOUALLEGUE B, et al.A reliable fault detection scheme for the AES hardware implementation[C]//International Symposium on Signal, Image, Video and Communications. Piscataway, NJ: IEEE Press, 2017: 47-52.
[13]	WEN L, JIANG W, JIANG K, et al.Detecting fault injection attacks on embedded real-time applications: A system-level perspective[C]//2015 IEEE 17th International Conference on High Performance Computing and Communications, 2015 IEEE 7th International Symposium on Cyberspace Safety and Security, and 2015 IEEE 12th International Conference on Embedded Software and Systems. Piscataway, NJ: IEEE Press, 2015: 700-705.
[14]	GILL H S.Selection of parameter 'r' in RC5 algorithm on the basis of prime number[C]//Engineering and Computational Sciences. Piscataway, NJ: IEEE Press, 2014: 6799519.
[15]	RIVEST R L.The RC5 encryption algorithm[C]//International Workshop on Fast Software Encryption. Berlin: Springer-Verlag, 1995: 86-96.
[16]	BEVI A R, SHESHU S S V, MALARVIZHI S.FPGA based pipelined architecture for RC5 encryption[C]//Second International Conference on Digital Information and Communication Technology and It's Applications. Piscataway, NJ: IEEE Press, 2012: 214-219.