基于任务映射的暗硅芯片功耗预算方法

李鑫; 李智; 周巍; 吴瑞祺; 唐浩然; 陈业航

doi:10.13700/j.bh.1001-5965.2021.0011

基于任务映射的暗硅芯片功耗预算方法

doi: 10.13700/j.bh.1001-5965.2021.0011

李鑫^1, ,,
李智¹,
周巍¹,
吴瑞祺²,
唐浩然³,
陈业航⁴

1.
西北工业大学电子信息学院, 西安 710072
2.
西北工业大学教育实验学院, 西安 710072
3.
西北工业大学软件学院, 西安 710072
4.
西北工业大学计算机学院, 西安 710072

基金项目:

国家自然科学基金 61501377

陕西省自然科学基础研究计划 2021JM-074

详细信息

通讯作者:
李鑫, E-mail: xinli@nwpu.edu.cn

中图分类号: TN47
计量
- 文章访问数: 466
- HTML全文浏览量: 105
- PDF下载量: 279
- 被引次数: 0
出版历程
- 收稿日期: 2021-01-11
- 录用日期: 2021-05-09
- 网络出版日期: 2021-06-02
- 整期出版日期: 2022-07-20

A power budgeting method for dark silicon chips based on task mapping

LI Xin^{1
, ,},
LI Zhi¹,
ZHOU Wei¹,
WU Ruiqi²,
TANG Haoran³,
CHEN Yehang⁴

1.
School of Electronics and Information, Northwestern Polytechnical University, Xi'an 710072, China
2.
Honors College, Northwestern Polytechnical University, Xi'an 710072, China
3.
School of Software, Northwestern Polytechnical University, Xi'an 710072, China
4.
School of Computer Science, Northwestern Polytechnical University, Xi'an 710072, China

Funds:

National Natural Science Foundation of China 61501377

Natural Science Basic Research Program of Shaanxi 2021JM-074

More Information

Corresponding author: LI Xin, E-mail: xinli@nwpu.edu.cn

摘要

摘要:
暗硅系统功耗预算问题可被归类为一种NP-hard问题，针对其存在的提高芯片均温与降低通信成本2个对立优化目标，提出了一种基于任务映射的暗硅芯片功耗预算方法。为降低计算复杂度，基于率先映射高通信量并对后续映射影响较小的任务的规则建立模型，将任务图转换为最大生成树的形式，以优先级值的大小决定任务进行映射的先后顺序。在稳态情况下逐个进行核心寻优，将排序后的任务放置于合适的核心位置，并以凸二次规划问题形式对已确定映射核心位置的功耗预算进行求解。实验表明：针对12开启核心的36核心系统，与经典的热安全功耗预算方法相比，所提方法将总功耗预算提高了11.8%，通信能耗降低了38.2%。
- 暗硅 /
- 功耗预算 /
- 任务映射 /
- 多核系统 /
- 动态热管理
Abstract:
The power budgeting for dark silicon systems can be regarded as a NP-hard problem. To achieve two opposite optimization objectives of improving chip average temperature and reducing communication cost, a power budgeting method based on task mapping for dark silicon chips is proposed. To reduce the computational complexity, a model is established to transform the task graph into a maximum spanning tree, based on the rule that the task with high throughput and less impact on subsequent mapping is mapped first. The priority value determines the mapping order of tasks. Then, the core-by-core optimization is carried out in a steady state. The sorted tasks are assigned to appropriate active cores. The power budgets of the identified active cores are solved in the form of convex quadratic programming. Experimental results show that compared with the classical thermal safe power budgeting method, the method proposed increases the total power budget by 11.8% and reduces the communication energy consumption by 38.2% for 36-core system with 12 active cores.
- dark silicon /
- power budget /
- task mapping /
- multicore system /
- dynamic thermal management

HTML全文

图 1 2D-Mesh拓扑结构

Figure 1. 2D-Mesh topology structure

下载: 全尺寸图片幻灯片

图 2 平面版图设计

Figure 2. 2D layout design

下载: 全尺寸图片幻灯片

图 3 任务映射示例

Figure 3. An example of task mapping

下载: 全尺寸图片幻灯片

图 4 任务映射方式

Figure 4. Task mapping method

下载: 全尺寸图片幻灯片

图 5 芯片的等效散热电路

Figure 5. Equivalent heat dissipation circuit of chip

下载: 全尺寸图片幻灯片

图 6 任务优先级排序流程

Figure 6. Flowchart of task priority ranking

下载: 全尺寸图片幻灯片

图 7 寻找第1个开启核心示意图

Figure 7. Diagram of finding the first active core

下载: 全尺寸图片幻灯片

图 8 本文功耗预算方法流程

Figure 8. Flowchart of the proposed power budgeting method

下载: 全尺寸图片幻灯片

图 9 相同暗硅比例系统功耗预算方法性能对比

Figure 9. Performance comparison of power budgeting methods under the same system of dark silicon percentages

下载: 全尺寸图片幻灯片

图 10 两种实际多媒体基准程序的通信任务图

Figure 10. Communication task graphs of two actual multimedia applications

下载: 全尺寸图片幻灯片

图 11 相同子任务数目的3种应用结果对比

Figure 11. Comparison of results of three applications with the same number of subtasks

下载: 全尺寸图片幻灯片

图 12 不同方法的代表性核心映射结果

Figure 12. Representative core mapping results using different methods

下载: 全尺寸图片幻灯片

图 13 不同方法的代表性核心映射所对应的温度分布

Figure 13. Temperature distribution corresponding to representative core mapping using different methods

下载: 全尺寸图片幻灯片

图 14 不同α值下MPEG-4功耗预算和AWMD变化趋势

Figure 14. Trends of power budget and AWMD for MPEG-4 with different α values

下载: 全尺寸图片幻灯片

表 1 三种方法总功耗预算与AWMD的计算结果

Table 1. Results of total power budget and AWMD using three methods

核心数	开启核心数	TSP方法^[5]		GDP方法^[7]		本文方法
核心数	开启核心数	功耗预算/W	AWMD	功耗预算/W	AWMD	功耗预算/W	AWMD
9	2	82.00	1.00	86.01	2.00	83.89	1.00
	4	128.13	1.47	137.69	2.00	134.52	1.02
	8	179.04	2.03	188.53	2.26	187.50	1.30
16	4	127.73	1.47	138.02	2.38	133.70	1.02
	8	179.78	2.17	199.80	2.70	193.94	1.41
	12	210.47	2.20	230.10	2.90	227.24	1.54
25	8	179.17	2.27	198.97	2.82	196.63	1.27
	12	211.70	2.49	239.15	3.61	235.97	1.69
	18	241.39	2.74	268.72	3.60	267.45	1.91
36	12	213.96	2.97	247.25	3.92	238.07	1.80
	18	242.30	3.29	281.56	4.21	276.37	2.27
	24	269.65	3.34	319.59	5.10	316.69	2.58
64	18	254.57	3.68	297.45	5.99	291.76	2.36
	24	265.01	4.33	319.35	6.39	311.45	2.63
	46	313.88	5.02	361.22	6.92	357.12	2.77

下载: 导出CSV

表 2 本文方法与其他方法提升效果比较(36核心系统)

Table 2. Comparison of improved performance between the proposed method and other methods (36 core system)

应用程序	功耗预算提升比例/%		AWMD减少比例/%
应用程序	本文方法vs TSP方法	本文方法vs GDP方法	本文方法vs TSP方法	本文方法vs GDP方法
tgff-12	11.27	-3.71	39.39	54.08
MWD	11.71	-3.33	35.41	56.77
MPEG-4	12.41	-2.72	39.86	59.08

下载: 导出CSV

参考文献(16)

[1]	ESMAEILZADEH H, BLEM E, AMANT R S, et al. Dark silicon and the end of multicore scaling[J]. IEEE Micro, 2011, 39(3): 365-376.
[2]	HAGHBAYAN M H, RAHMANI A M, WELDEZION A Y, et al. Dark silicon aware power management for manycore systems under dynamic workloads[C]//Proceedings of the 32nd IEEE International Conference on Computer Design. Piscataway: IEEE Press, 2014: 509-512.
[3]	黄柯衡, 张正鸿, 王海, 等. 基于混合优化的多核处理器动态热管理方法[J]. 电子工艺技术, 2018, 39(2): 71-75. https://www.cnki.com.cn/Article/CJFDTOTAL-DZGY201802003.htm HUANG K H, ZHANG Z H, WANG H, et al. Hybrid dynamic thermal management method for multi-core microprocessors[J]. Electronics Process Technology, 2018, 39(2): 71-75(in Chinese). https://www.cnki.com.cn/Article/CJFDTOTAL-DZGY201802003.htm
[4]	孙奥林, 徐奇, 陈松. 暗硅多核系统芯片资源调度算法[J]. 计算机辅助设计与图形学学报, 2017, 29(6): 1145-1154. doi: 10.3969/j.issn.1003-9775.2017.06.021 SUN A L, XU Q, CHEN S. Resource scheduling algorithm for multi-core system chip with dark silicon[J]. Journal of Computer-Aided Design & Computer Graphics, 2017, 29(6): 1145-1154(in Chinese). doi: 10.3969/j.issn.1003-9775.2017.06.021
[5]	PAGANI S, KHDR H, CHEN J J, et al. Thermal safe power (TSP): Efficient power budgeting for heterogeneous manycore systems in dark silicon[J]. IEEE Transactions on Computers, 2017, 66(1): 147-162. doi: 10.1109/TC.2016.2564969
[6]	WANG H, ZHANG M, TAN S X D, et al. New power budgeting and thermal management scheme for multi-core systems in dark silicon[C]//Proceedings of the 29th IEEE International System-on-Chip Conference. Piscataway: IEEE Press, 2016: 344-349.
[7]	WANG H, TANG D Y, ZHANG M, et al. GDP: A greedy based dynamic power budgeting method for multi/many-core systems in dark silicon[J]. IEEE Transactions on Computers, 2019, 68(4): 526-541. doi: 10.1109/TC.2018.2875986
[8]	AGYEMAN M O, AHMADINIA A, BAGHERZADEH N. Performance and energy aware inhomogeneous 3D networks-on-chip architecture generation[J]. IEEE Transactions on Parallel and Distributed Systems, 2016, 27(6): 1756-1769. doi: 10.1109/TPDS.2015.2457444
[9]	AGYEMAN M O, TONG K F, MAK T. Towards reliability and performance-aware wireless network-on-chip design[C]//Proceedings of the 2015 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems. Piscataway: IEEE Press, 2015: 205-210.
[10]	RAPP M, SAGI M, PATHANIA A, et al. Power- and cache-aware task mapping with dynamic power budgeting for many-cores[J]. IEEE Transactions on Computers, 2020, 69(1): 1-13.
[11]	KANDURI A, HAGHBAYAN M H, RAHMANI A M, et al. Dark silicon aware runtime mapping for many-core systems: A patterning approach[C]//Proceedings of the 33rd IEEE International Conference on Computer Design. Piscataway: IEEE Press, 2015: 573-580.
[12]	MAQSOOD T, ALI S, MALIK S U R, et al. Dynamic task mapping for network-on-chip based systems[J]. Journal of Systems Architecture, 2015, 61(7): 293-306.
[13]	WANG X H, SINGH A K, LI B, et al. Bubble budgeting: Throughput optimization for dynamic workloads by exploiting dark cores in many core systems[J]. IEEE Transactions on Computers, 2018, 67(2): 178-192. doi: 10.1109/TC.2017.2735967
[14]	LI B, WANG X H, SINGH A K, et al. On runtime communication and thermal-aware application mapping and defragmentation in 3D NoC systems[J]. IEEE Transactions on Parallel and Distributed Systems, 2019, 30(12): 2775-2789.
[15]	HAGHBAYAN M H, KANDURI A, RAHMANI A M, et al. MapPro: Proactive runtime mapping for dynamic workloads by quantifying ripple effect of applications on networks-on-chip[C]//Proceedings of the 9th International Symposium on Networks-on-Chip. New York: ACM, 2015: 1-8.
[16]	FATTAH M, DANESHTALAB M, LILJEBERG P, et al. Smart hill climbing for agile dynamic mapping in many-core systems[C]//Proceedings of the 50th Annual Design Automation Conference. Piscataway: IEEE Press, 2013: 1-6.