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一种FPGA实现的复杂背景红外小目标检测网络

周海 侯晴宇 卞春江 冯水春 刘一腾

周海,侯晴宇,卞春江,等. 一种FPGA实现的复杂背景红外小目标检测网络[J]. 北京航空航天大学学报,2023,49(2):295-310 doi: 10.13700/j.bh.1001-5965.2021.0221
引用本文: 周海,侯晴宇,卞春江,等. 一种FPGA实现的复杂背景红外小目标检测网络[J]. 北京航空航天大学学报,2023,49(2):295-310 doi: 10.13700/j.bh.1001-5965.2021.0221
ZHOU H,HOU Q Y,BIAN C J,et al. An infrared small target detection network under various complex backgrounds realized on FPGA[J]. Journal of Beijing University of Aeronautics and Astronautics,2023,49(2):295-310 (in Chinese) doi: 10.13700/j.bh.1001-5965.2021.0221
Citation: ZHOU H,HOU Q Y,BIAN C J,et al. An infrared small target detection network under various complex backgrounds realized on FPGA[J]. Journal of Beijing University of Aeronautics and Astronautics,2023,49(2):295-310 (in Chinese) doi: 10.13700/j.bh.1001-5965.2021.0221

一种FPGA实现的复杂背景红外小目标检测网络

doi: 10.13700/j.bh.1001-5965.2021.0221
基金项目: 中国科学院青年创新促进会资助项目(E0293401)
详细信息
    通讯作者:

    E-mail: houqingyu@126.com

  • 中图分类号: V249.32+6;TP391;TN215

An infrared small target detection network under various complex backgrounds realized on FPGA

Funds: Youth Innovation Promotion Association CAS (E0293401)
More Information
  • 摘要:

    红外(IR)小目标检测算法具有检测率高、虚警率低、实时性好等优点在红外遥感领域有重要的应用价值。由于复杂背景下小目标对比度低和信噪比(SNR)低,传统红外小目标检测算法难以保证检测性能。在强鲁棒性的红外小目标检测网络(RISTDnet)基础上,面向更为多样的目标结构特征和更高的实时处理性能要求,提出一种增强型红外小目标检测网络(EISTDnet)与其基于现场可编程逻辑门阵列(FPGA)高性能并行处理的算法。EISTDnet构造了手工特征算法与卷积神经网络相结合的多尺度小目标特征提取框架,采用多级展开思路对卷积核尺寸进行归一化设计,并通过数据深度复用和多维循环并行展开有效提高推理阶段实时处理性能。实验结果表明:采用单片FPGA实现的EISTDnet能够快速实时检测复杂背景下不同大小、低信噪比的小目标,与现有5种算法相比在10−3低虚警率下平均检测率提升49.5%,与RISTDnet相比,在实时处理速度提高1.33倍的优势下,对低信噪比条状小目标检测率提升29.4%,所提算法具有更好的有效性和鲁棒性。

     

  • 图 1  低信噪比条状小目标示意图[17]

    Figure 1.  Small strip target with low SNR[17]

    图 2  EISTDnet定权特征提取卷积核

    Figure 2.  EISTDnet feature extraction convolution kernel with fixed weight

    图 3  卷积核尺寸多级串联优化

    Figure 3.  Multi-stage series optimization of convolution kernel size

    图 4  EISTDnet网络结构

    Figure 4.  Network structure of EISTDnet

    图 5  特征拼接子网络细节

    Figure 5.  Detail of feature connection sub-network

    图 6  特征映射层细节

    Figure 6.  The detail of feature mapping layer

    图 7  多尺度定权特征提取数据复用关系示意图

    Figure 7.  Multi-scale feature extraction data reuse relationship with fixed weight

    图 8  EISTDnet新增定权特征提取数据复用关系示意图

    Figure 8.  New feature extraction data reuse relationship with fixed weight of EISTDnet

    图 9  定权特征提取模块FPGA实现框图

    Figure 9.  FPGA implementation block diagram of fixed-weight feature extraction module

    图 10  卷积运算4层循环示意图

    Figure 10.  Four-layer loop diagram of convolution operation

    图 11  循环一维展开示意图

    Figure 11.  One-dimensional unfolding loop diagram

    图 12  EISTDnet二维循环展开示意图

    Figure 12.  Two-dimensional loop unfolding diagram of EISTDnet

    图 13  多级缓存示意图

    Figure 13.  Multi-level cache diagram

    图 14  循环计算顺序示意图

    Figure 14.  Diagram of cyclic calculation sequence

    图 15  变权卷积网络实时高性能并行处理架构示意图

    Figure 15.  Real-time high-performance parallel processing architecture of variable-weight convolutional networks

    图 16  测试序列典型帧示意图

    Figure 16.  Diagram of test sequence typical frames

    图 17  高性能FPGA处理板

    Figure 17.  Self-developed image processing board

    图 18  自测试验证系统

    Figure 18.  Self-test verification system

    图 19  不同算法检测结果对比

    Figure 19.  Detection results of different methods

    图 20  不同算法ROC曲线对比

    Figure 20.  ROC curves of different methods

    图 21  不同信噪比下EISTDnet与RISTDnet条状弱小目标检测率曲线

    Figure 21.  Stripe dim targets detection rate curves of different SNR between EISTDnet and RISTDnet

    图 22  EISTDnet网络在FPGA内处理流水线示意图

    Figure 22.  Schematic diagram of EISTDnet network processing pipeline in FPGA

    图 23  EISTDnet 的FPGA实现仿真波形

    Figure 23.  FPGA simulation waveform of EISTDnet

    图 24  RISTDnet 的FPGA实现仿真波形

    Figure 24.  FPGA simulation waveform of RISTDnet

    表  1  EISTDnet网络参数

    Table  1.   EISTDnet network parameters

    层编号卷积核
    数量
    卷积核
    尺寸/步长
    输出特征图
    尺寸
    特征提取512×640
    Conv1.1243×3/1512×640
    Conv1.2243×3/1512×640
    Conv1.3243×3/1512×640
    Conv1.4243×3/1512×640
    Conv1.5323×3/1512×640
    Pool12×2/2256×320
    Conv2.1323×3/1256×320
    Conv2.2323×3/1256×320
    Conv2.3643×3/1256×320
    Pool22×2/2128×160
    Conv3.1643×3/1128×160
    Conv3.21283×3/1128×160
    Pool32×2/264×80
    Conv42563×3/164×80
    Conv5643×3/164×80
    下载: 导出CSV

    表  2  EISTDnet与RISTDnet运算操作数比对

    Table  2.   Comparison of operands between EISTDnet and RISTDnet

    网络改进阶段运算操作数
    RISTDnet69999411200
    EISTDnet强化多尺度特征90460323840
    EISTDnet卷积网络轻量化33919795200
    下载: 导出CSV

    表  3  图像读取与运算操作比对

    Table  3.   Image reading and operation comparison

    算法像素读取次数运算操作数
    优化前607846400629473280
    优化后3964928097648640
    降低比例/%6.5215.51
    下载: 导出CSV

    表  4  测试序列典型帧与数量

    Table  4.   Typical frames and number of test sequences

    项目测试序列 1测试序列 2测试序列 3
    典型帧图16(a)图16(b)图16(c)
    总帧数141218451660
    下载: 导出CSV

    表  5  EISTDnet与RISTDnet目标检测性能对比

    Table  5.   Comparison of target detection performance between EISTDnet and RISTDnet %

    项目EISTDnetRISTDnet
    测试序列166.9763.81
    测试序列250.9948.65
    测试序列352.7650.25
    下载: 导出CSV

    表  6  EISTDnet与RISTDnet条状弱小目标检测性能对比

    Table  6.   Comparison of stripe dim target detection performance between EISTDnet and RISTDnet

    项目EISTDnet
    目标数/检出数
    RISTDnet
    目标数/检出数
    测试序列150/3150/15
    测试序列250/2450/12
    测试序列350/2750/14
    平均检测率/%56.727.3
    下载: 导出CSV

    表  7  FPGA资源利用率

    Table  7.   FPGA resource utilization

    资源BRAMDSP硬核触发器查找表
    使用资源27463258755915360141
    可利用资源29403600866400433200
    利用率/%93918783
    下载: 导出CSV
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出版历程
  • 收稿日期:  2021-04-29
  • 录用日期:  2021-06-06
  • 网络出版日期:  2021-08-09
  • 整期出版日期:  2023-02-28

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