An infrared small target detection network under various complex backgrounds realized on FPGA
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摘要:
红外（IR）小目标检测算法具有检测率高、虚警率低、实时性好等优点在红外遥感领域有重要的应用价值。由于复杂背景下小目标对比度低和信噪比（SNR）低，传统红外小目标检测算法难以保证检测性能。在强鲁棒性的红外小目标检测网络（RISTDnet）基础上，面向更为多样的目标结构特征和更高的实时处理性能要求，提出一种增强型红外小目标检测网络（EISTDnet）与其基于现场可编程逻辑门阵列（FPGA）高性能并行处理的算法。EISTDnet构造了手工特征算法与卷积神经网络相结合的多尺度小目标特征提取框架，采用多级展开思路对卷积核尺寸进行归一化设计，并通过数据深度复用和多维循环并行展开有效提高推理阶段实时处理性能。实验结果表明：采用单片FPGA实现的EISTDnet能够快速实时检测复杂背景下不同大小、低信噪比的小目标,与现有5种算法相比在10−3低虚警率下平均检测率提升49.5%，与RISTDnet相比，在实时处理速度提高1.33倍的优势下，对低信噪比条状小目标检测率提升29.4%，所提算法具有更好的有效性和鲁棒性。
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关键词:
- 卷积神经网络 /
- 红外小目标 /
- 目标检测 /
- 现场可编程逻辑门阵列 /
- 实时
Abstract:The infrared (IR) small target detection algorithm with high detection rate, low false alarm rate and good real-time performance has important application value in the field of IR remote sensing. Traditional IR small targets detection algorithms cannot guarantee the detection performance due to the low contrast and low signal-to-noise ratio (SNR) of small targets under various complex backgrounds. Based on robust infrared small target detection network (RISTDnet) proposed, for more diverse target structure characteristics and higher real-time processing performance requirements, an enhanced infrared small target detection network (EISTDnet) and its field programmable logic gate array (FPGA) based high-performance parallel processing method are proposed. In EISTDnet, a multi-scale small target feature extraction framework that combines manual feature methods and convolutional neural networks is constructed, the size of the convolution kernel is normalized by the idea of multi-level expansion, and real-time processing performance in the inference stage is effectively improved through deep data reuse and multi-dimensional loop parallel unfolding. Experimental results show that the EISTDnet realized on a single FPGA can quickly detect small targets with different sizes and low SNR in various complex backgrounds in real time. Compared with the existing 5 algorithms, the average detection rate is increased by 49.5% with a low false alarm rate of 10−3. Compared with RISTDnet, the real-time processing speed is increased by 1.33 times, and the detection rate of low SNR strip small targets is increased by 29.4%. EISTDnet has better effectiveness and robustness.
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图 2 EISTDnet定权特征提取卷积核
Figure 2. EISTDnet feature extraction convolution kernel with fixed weight
图 7 多尺度定权特征提取数据复用关系示意图
Figure 7. Multi-scale feature extraction data reuse relationship with fixed weight
图 8 EISTDnet新增定权特征提取数据复用关系示意图
Figure 8. New feature extraction data reuse relationship with fixed weight of EISTDnet
图 9 定权特征提取模块FPGA实现框图
Figure 9. FPGA implementation block diagram of fixed-weight feature extraction module
图 15 变权卷积网络实时高性能并行处理架构示意图
Figure 15. Real-time high-performance parallel processing architecture of variable-weight convolutional networks
图 21 不同信噪比下EISTDnet与RISTDnet条状弱小目标检测率曲线
Figure 21. Stripe dim targets detection rate curves of different SNR between EISTDnet and RISTDnet
图 22 EISTDnet网络在FPGA内处理流水线示意图
Figure 22. Schematic diagram of EISTDnet network processing pipeline in FPGA
表 1 EISTDnet网络参数
Table 1. EISTDnet network parameters
层编号 卷积核
数量卷积核
尺寸/步长输出特征图
尺寸特征提取 512×640 Conv1.1 24 3×3/1 512×640 Conv1.2 24 3×3/1 512×640 Conv1.3 24 3×3/1 512×640 Conv1.4 24 3×3/1 512×640 Conv1.5 32 3×3/1 512×640 Pool1 2×2/2 256×320 Conv2.1 32 3×3/1 256×320 Conv2.2 32 3×3/1 256×320 Conv2.3 64 3×3/1 256×320 Pool2 2×2/2 128×160 Conv3.1 64 3×3/1 128×160 Conv3.2 128 3×3/1 128×160 Pool3 2×2/2 64×80 Conv4 256 3×3/1 64×80 Conv5 64 3×3/1 64×80 
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表 2 EISTDnet与RISTDnet运算操作数比对
Table 2. Comparison of operands between EISTDnet and RISTDnet
网络改进阶段 运算操作数 RISTDnet 69999411200 EISTDnet强化多尺度特征 90460323840 EISTDnet卷积网络轻量化 33919795200
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表 3 图像读取与运算操作比对
Table 3. Image reading and operation comparison
算法 像素读取次数 运算操作数 优化前 607846400 629473280 优化后 39649280 97648640 降低比例/% 6.52 15.51
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表 4 测试序列典型帧与数量
Table 4. Typical frames and number of test sequences
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表 5 EISTDnet与RISTDnet目标检测性能对比
Table 5. Comparison of target detection performance between EISTDnet and RISTDnet
% 项目 EISTDnet RISTDnet 测试序列1 66.97 63.81 测试序列2 50.99 48.65 测试序列3 52.76 50.25
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表 6 EISTDnet与RISTDnet条状弱小目标检测性能对比
Table 6. Comparison of stripe dim target detection performance between EISTDnet and RISTDnet
项目 EISTDnet
目标数/检出数RISTDnet
目标数/检出数测试序列1 50/31 50/15 测试序列2 50/24 50/12 测试序列3 50/27 50/14 平均检测率/% 56.7 27.3
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表 7 FPGA资源利用率
Table 7. FPGA resource utilization
资源 BRAM DSP硬核 触发器 查找表 使用资源 2746 3258 755915 360141 可利用资源 2940 3600 866400 433200 利用率/% 93 91 87 83
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