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摘要:
自主定位是移动机器人实现完全自主移动的基础，其中的关键技术同步定位与建图（SLAM）备受关注。惯性测量单元（IMU）因具有不受外界环境影响的优势广泛应用在SLAM系统中。SLAM后端使用非线性优化方法优化IMU的状态，实际应用中存在实时性差、能耗高的问题。为此，在现场可编程门阵列（FPGA）平台上设计了用于IMU状态优化的加速器。分析算法的数据流程实现电路和数据复用，充分利用算法特有的稀疏特性实现计算简化和存储压缩，同时对于计算量最大的解方程步骤，硬件电路采用可配置设计，通过改变该电路模块的配置使加速器实现性能、功耗和资源使用的折中，满足不同场景的要求。在Xilinx ZC706平台上的实验结果表明：相比于Intel i5-8250U和Arm Cortex-A57处理器，所设计的加速器应用于高性能场景的电路时，可以达到26.7倍和87倍的加速效果；应用于低功耗场景的电路时，加速效果分别为17.4倍和53.7倍；不同配置的电路均可节约能耗90%以上。
Abstract:Mobile robots to localize themselves is a prerequisite for full ego-motion. Simultaneous localization and mapping (SLAM), a key localization technology, has gained a lot of attention. An inertial measurement unit (IMU) is widely used in SLAM systems for its advantage of not being affected by the external environment. The backend of SLAM uses nonlinear optimization methods to optimize IMU states. There are problems of poor real-time performance and high energy consumption. This paper designs an accelerator for IMU state optimization on the field programmable gate array (FPGA) platform. Firstly, by analyzing the data flow of the algorithm, the accelerator realizes circuits and data reuse. Secondly, by making use of the sparse characteristics, calculation simplification and storage compression are realized. Finally, the hardware employs a configurable design for the equation solving step, which requires the most computation. By changing the configuration, the accelerator can achieve a compromise between performance, power consumption, and resource utilization. The experimental results on the Xilinx ZC706 platform indicate that the accelerator designed for high-performance scenarios can achieve 26.7 times and 87 times performance improvement compared to Intel i5-8250U and Arm Cortex-A57 processors; the performance improvement of low-power scenario accelerator is 17.4 times and 53.7 times, respectively. Besides, different configurations can save more than 90% of energy.
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图 4 误差、雅可比和成本计算电路及配置模式
Figure 4. Error, Jacobian and cost calculation circuit and its configuration modes
图 5 误差、雅可比和成本计算阶段1电路
Figure 5. Stage one of error, Jacobian and cost calculation circuit
图 7 在20个和80个优化状态下的存储优化效果
Figure 7. Storage optimization results with 20 and 80 optimization states
图 8 乔可斯基分解算法线性方程组求解电路
Figure 8. Cholesky decomposition linear equation solving circuit
表 1 硬件设计的资源消耗
Table 1. Resource utilization of hardware design
电路 资源数 占比/% 查找表
（LUT）触发器
（FF）块随机存取存储器
（BRAM）数字信号处理
单元（DSP）查找表
（LUT）触发器
（FF）块随机存取存储器
（BRAM）数字信号处理
单元（DSP）C1 29057 29407 86.5 278 13.3 6.7 15.9 30.9 C2 44229 41840 131.5 458 20.2 9.6 24.1 50.9 C3 59617 54007 176.5 638 27.3 12.4 32.4 70.9 
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表 2 软硬件实现的性能比较
Table 2. Performance comparison between hardware and software implementations
状态数目 执行时间/ms FPGA加速比 x86 TX1 C1 C2 C3 x86 vs C1 x86 vs C2 x86 vs C3 TX1 vs C1 TX1 vs C2 TX1 vs C3 N=20 19.09 41.38 0.84 0.65 0.59 22.73 29.37 32.36 49.26 63.66 70.14 N=50 82.59 461.18 27.87 15.32 11.16 2.96 5.39 7.40 16.55 30.10 41.32 N=80 126.89 662.65 60.33 32.05 22.64 2.10 3.96 5.60 10.98 20.68 29.27 平均 76.19 388.40 29.68 16.01 11.46 9.26 12.91 15.12 25.60 38.15 46.91
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表 3 能耗对比
Table 3. Comparison of energy consumption
mJ 状态数目 硬件能耗 软件能耗 C1 C2 C3 x86 TX1 N=20 1.93 1.92 2.22 286.35 207.73 N=50 63.91 45.29 41.95 1238.85 2315.12 N=80 138.34 94.74 85.10 1903.35 3326.50
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