14 nm pFinFET器件抗单粒子辐射的加固方法

史柱; 王斌; 杨博; 赵雁鹏; 惠思源; 刘文平

doi:10.13700/j.bh.1001-5965.2022.0071

14 nm pFinFET器件抗单粒子辐射的加固方法

doi: 10.13700/j.bh.1001-5965.2022.0071

史柱¹,
王斌^{1, 2},
杨博^{1, 2},
赵雁鹏¹,
惠思源^{1, 2},
刘文平^{1, 2, ,}

1.
西安微电子技术研究所，西安 710065
2.
抗辐射集成电路国防科技重点实验室，西安 710065

基金项目: 国家科技重大专项(2020002-047)

详细信息

通讯作者:
E-mail：liu-wp@163.com

中图分类号: V216.5⁺1
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出版历程
- 收稿日期: 2022-02-14
- 录用日期: 2022-04-16
- 网络出版日期: 2022-04-28
- 整期出版日期: 2023-12-29

Single-event radiation hardening method for 14 nm pFinFET device

SHI Zhu¹,
WANG Bin^{1, 2},
YANG Bo^{1, 2},
ZHAO Yanpeng¹,
HUI Siyuan^{1, 2},
LIU Wenping^{1, 2
, ,}

1.
Xi’an Microelectronics Technology Institute，Xi’an 710065，China
2.
National Key Laboratory of Science and Technology on Radiation-Hardened Integrated Circuits，Xi’an 710065，China

Funds: National Science and Technology Major Project (2020002-047)

More Information

Corresponding author: E-mail：liu-wp@163.com

摘要

摘要:
为探究先进互补金属氧化物半导体（CMOS）工艺在空间应用中的可靠性问题，研究14 nm工艺下P型沟道鳍式场效应晶体管(pFinFET)器件中的抗单粒子瞬态(SET)加固策略。通过在器件中插入平行于鳍方向的重掺杂N型沟槽(Ntie)和P型沟槽(Ptie)来减缓SET的影响。三维TCAD仿真结果表明：加固之后器件的抗SET特性和沟槽本身的偏置条件相关。当重掺杂沟槽处于零偏状态时，抗辐射加固的性能最好，SET脉冲宽度降低程度可达40%左右；然而，当处于反偏状态时，由于特殊的电荷收集过程的存在，使得SET脉冲幅度反而会明显增大，脉冲宽度减小程度并不明显。此外，还研究沟槽面积、间距及掺杂浓度对pFinFET中的SET脉冲宽度的影响，得到提高抗SET效果的加固方法。
- 鳍式场效应晶体管 /
- 单粒子瞬态 /
- 器件 /
- 辐射加固 /
- 工艺
Abstract:
In order to investigate the reliability of advanced complementary metal-oxide-semiconductor (CMOS) processes for space applications, a hardening strategy against single-event transient (SET) is investigated in P-channel fin field-effect transistor (pFinFET) devices at 14 nm. The effects of SETs are mitigated by inserting heavily doped N-type trenches (Ntie) and P-type trenches (Ptie) parallel to the fin direction in the device. Three-dimensional TCAD simulations show that the resistance to SET of the device by introducing trenches is related to the bias conditions of the trenches themselves. The SET voltage pulse amplitude increases significantly when the trenches are in the reverse-bias state due to the presence of a special charge collection process, in addition to a slight decrease in pulse width compared to the unhardened devices, which results in the best radiation-hardening performance when the trenches are at zero bias and have a reduction in SET pulse width of about 40%. Besides, the impact of trench area, spacing, and doping concentration on the SET pulse width in the pFinFET is also investigated, obtaining the device parameters with the best resistance to SET.
- fin field-effect transistor /
- single-event transient /
- device /
- radiation hardening /
- process

HTML全文

图 1 FinFET器件中引入的电场^[6]

Figure 1. The introduced electric field in FinFET device^[6]

下载: 全尺寸图片幻灯片

图 2 插入了Ntie和Ptie的pFinFET器件结构

Figure 2. Structure of pFinFET device with inserted Ntie and Ptie

下载: 全尺寸图片幻灯片

图 3 混合仿真反相器

Figure 3. Mixed-mode simulation inverter

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图 4 不同器件结构和偏置条件下的pFinFET单粒子脉冲电压

Figure 4. SET pulses of pFinFET at different structures and bias conditions

下载: 全尺寸图片幻灯片

图 5 辐射之后的pFinFET器件各端口电流及其主要成分

Figure 5. Currents and their main components at each port of pFinFET device after radiation

下载: 全尺寸图片幻灯片

图 6 Ntie和Ptie处于反偏状态下的加固pFinFET器件辐照前后的电流

Figure 6. Currents in hardened pFinFET device before and after radiationwith Ntie and Ptie in reverse bias state

下载: 全尺寸图片幻灯片

图 7 粒子入射5 ps后器件内部电势分布

Figure 7. Potential distribution inside device after 5 ps of particle incidence

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图 8 SET测试电路基本结构

Figure 8. Basic structure of SET test circuit

下载: 全尺寸图片幻灯片

表 1 不同器件产生的SET脉冲宽度和幅值

Table 1. SET pulses width and amplitude generated by different devices

器件	脉宽/ps	幅度/V
V_LET=1，未加固	12.0	0.95
V_LET=2，未加固	14.7	0.98
V_LET=3，未加固	16.0	0.99
V_LET=1，反偏	10.5	1.33
V_LET=2，反偏	12.7	1.48
V_LET=3，反偏	13.6	1.47
V_LET=1，零偏	7.2	0.77
V_LET=2，零偏	8.8	0.78
V_LET=3，零偏	9.8	0.78

下载: 导出CSV

表 2 沟槽的参数变化对pFinFET中脉冲宽度的影响

Table 2. Effect of parameter variation of trenches on pulse width in pFinFET

参数	脉宽/ps	脉宽变化
本文仿真条件（见2.1节）	7.2
掺杂浓度提高10倍	7	减小
掺杂浓度提高100倍	6.9	减小
表面积减半	7	减小
表面积加倍	7.3	增大
与鳍的距离减半	6.5	减小
与鳍的距离加倍	7.9	增大

下载: 导出CSV

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