基于指令扩展的RISC-V可配置故障注入检测方法

刘强; 李一可

doi:10.13700/j.bh.1001-5965.2022.0995

基于指令扩展的RISC-V可配置故障注入检测方法

doi: 10.13700/j.bh.1001-5965.2022.0995

刘强^{1, 2, ,},
李一可^{1, 2}

1.
天津大学微电子学院，天津 300072
2.
天津市成像与感知微电子技术重点实验室，天津 300072

基金项目:

国家自然科学基金(61974102)

详细信息

通讯作者:
E-mail：qiangliu@tju.edu.cn

中图分类号: TN407
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- 文章访问数: 621
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- 被引次数: 0
出版历程
- 收稿日期: 2022-12-15
- 录用日期: 2023-02-24
- 网络出版日期: 2023-03-09
- 整期出版日期: 2025-01-31

Configurable fault injection detection method for RISC-V based on instruction extension

LIU Qiang^{1, 2
, ,},
LI Yike^{1, 2}

1.
School of Microelectronics，Tianjin University，Tianjin 300072，China
2.
Tianjin Key Laboratory of Imaging and Sensing Microelectronic Technology，Tianjin 300072，China

Funds:

National Natural Science Foundation of China (61974102)

More Information

Corresponding author: E-mail：qiangliu@tju.edu.cn

摘要

摘要:
针对处理器运行时受到故障攻击出现的数据流错误，提出了一种面向RISC-V处理器微架构的模式可配置故障注入检测方法。该方法基于RISC-V指令集架构，利用其可扩展性添加带模式配置的自定义算术逻辑运算指令和控制与状态寄存器，以软硬件结合的方式同时实现算术逻辑运算和故障注入检测。在软件层面，通过写寄存器指令将配置信息写入自定义的控制与状态寄存器，配置自定义指令的故障注入检测模式，包括信息冗余和时间冗余2种故障注入检测模式及其参数；在硬件层面，实现了支持模式可配置故障注入检测方法的RISC-V处理器微架构。采用仿真器命令模拟故障注入，验证扩展后的RISC-V处理器的功能正确性与故障注入检测能力。实验结果表明：当信息冗余模式和时间冗余模式的应用频率相同时，模式可配置方法相较于单信息冗余方法，平均故障检测率提高13.34%，引入4.4%的平均资源开销；相较于单时间冗余方法，降低了8.24%的平均时间开销，故障检测率降低了13.33%。所提模式可配置方法可以实现故障检测率和时间开销的折中，适用于不同安全性和性能需求的应用场景。
- 硬件安全 /
- 故障注入攻击对策 /
- 故障注入检测 /
- RISC-V处理器 /
- 指令扩展
Abstract:
For data flow errors caused by fault attacks during processor operation, this paper designed a configurable fault injection detection method based on RISC-V processor microarchitecture. Based on the RISC-V instruction set architecture, this method took advantage of its expandability to add custom arithmetic logic instructions with mode configuration and control and state registers and realized the arithmetic logic operation and fault detection simultaneously by the combination of hardware and software. At the software level, configuration information was written to the customized control and state register by register access instructions to configure the fault detection modes of the customized instructions, including information and temporal redundancy modes and their parameters. At the hardware level, a RISC-V processor microarchitecture supporting configurable fault injection detection was implemented. Finally, the simulator command was used to simulate the fault injection, and the functional correctness and fault injection detection capability of the extended RISC-V processor were verified. The experimental results show that compared to the single information redundancy method, when the information redundancy mode and temporal redundancy mode are applied with the same frequency, the proposed configurable method improves the average fault detection rate by 13.34% with an average resource overhead of 4.4%. Compared to the single temporal redundancy method, it reduces the average time overhead by 8.24% with a 13.33% decrease in fault detection rate. The proposed configurable method can achieve a compromise between fault detection rate and time overhead and be applied in application scenarios with different security and performance requirements.
- hardware security /
- countermeasure for fault injection attacks /
- fault injection detection /
- RISC-V processor /
- instruction extension

HTML全文

图 1 RISC-V自定义指令扩展流程

Figure 1. Customized instruction extension flow of RISC-V

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图 2 基于信息冗余的故障注入检测方法

Figure 2. Fault injection detection method based on information redundancy

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图 3 基于时间冗余的故障注入检测方法

Figure 3. Fault injection detection method based on temporal redundancy

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图 4 模式可配置故障注入检测方法示意图

Figure 4. Mode configurable fault injection detection method

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图 5 自定义寄存器类型32位整数指令

Figure 5. Customized register-type 32-bit integer instruction

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图 6 自定义立即数类型32位整数指令

Figure 6. Customized immediate-type 32-bit integer instruction

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图 7 故障注入检测模式可配置RISC-V处理器微架构

Figure 7. Microarchitecture of RISC-V processor with configurable fault injection detection mode

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图 8 信息冗余模式实现

Figure 8. Information redundancy mode implementation

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图 9 时间冗余模式实现

Figure 9. Temporal redundancy mode implementation

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图 10 添加复算控制的取指单元

Figure 10. Instruction fetch unit with re-fetch control

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图 11 故障注入模拟测试程序示意图

Figure 11. Fault injection simulation test procedure

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图 12 故障注入时序示意图

Figure 12. Fault injection timing

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图 13 模拟故障注入实验结果

Figure 13. Experimental results of simulated fault injection

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表 1 不同故障注入检测方法时间开销

Table 1. Time overhead for different fault injection detection methods

方法	时间开销/时钟周期数
方法	User PIN 1	User PIN 2	User PIN 3	User PIN 4
信息冗余	83	128	179	236
时间冗余（复算单次）	82	142	199	247
时间冗余（复算双次）	96	159	228	300
模式可配置（MREPLY = 01）	78	135	186	235
模式可配置（MREPLY = 10）	86	143	203	263
模式可配置（MREPLY = 11）	82	145	211	277

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表 2 不同故障注入检测方法资源开销

Table 2. Resource overhead for different fault injection detection methods

方法	LUT	FF	数字信号处理器	总可编程逻辑资源
zero-riscy处理器	3250	1930	1	5180
信息冗余（g = 32）	4004	2038	1	6042
信息冗余（g = 16）	4098	2065	1	6163
信息冗余（g = 8）	4035	2138	1	6173
时间冗余（复算单次）	3598	2033	1	5631
时间冗余（复算双次）	3530	2034	1	5564
模式可配置（g = 32）	4261	2080	1	6341
模式可配置（g = 16）	4313	2112	1	6425
模式可配置（g = 8）	4246	2175	1	6421

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