SRAM型FPGA多层级软错误防护技术研究进展

陈雷; 王卓立; 王硕; 周婧; 田春生; 庞永江

doi:10.13700/j.bh.1001-5965.2023.0587

SRAM型FPGA多层级软错误防护技术研究进展

doi: 10.13700/j.bh.1001-5965.2023.0587

北京微电子技术研究所，北京 100076

基金项目:

国家科技重大专项(2009ZYHJ0005)；国家自然科学基金(62374138)

详细信息

通讯作者:
E-mail：chenleinpu@vip.126.com

中图分类号: TN47；TP301；V443
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- 被引次数: 0
出版历程
- 收稿日期: 2023-09-14
- 录用日期: 2023-12-22
- 网络出版日期: 2024-03-07
- 整期出版日期: 2025-11-25

Survey of multi-level soft error mitigation techniques for SRAM-based FPGAs

Beijing Microelectronics Technology Institute，Beijing 100076，China

Funds:

National Science and Technology Major Project (2009ZYHJ0005) ; National Natural Science Foundation of China (62374138)

More Information

Corresponding author: E-mail：chenleinpu@vip.126.com

摘要

摘要:
静态随机存取存储器(SRAM)型FPGA具有开发成本低、设计周期短、通用性广等一系列优点，被广泛应用于航天、军事、高能核物理和地面通信等领域，这些应用的特殊性对FPGA器件的抗辐射性能提出了额外的需求，研究SRAM型FPGA的软错误防护方法，进而提升系统可靠性变得迫在眉睫。基于此，按硬件级别、系统级别和软件级别对各类抗辐射优化技术进行概述，梳理硬件防护、三模冗余(TMR)、动态刷新重配置、设计实现算法优化等主流技术，对各项技术的优势和劣势进行分析，并阐述使用原位容错方法作为补充技术，对三模冗余加动态刷新重配置技术后的FPGA设计进行进一步加固的可行性和必要性。对机器学习技术在抗辐射优化中的应用探索做了总结和展望，并对基于强化学习的软件容错方法的架构进行了描述，以希望为进一步完善FPGA软件抗辐射措施提供技术支持，为抗辐射加固及相关领域的研究人员提供参考。
- FPGA /
- 单粒子效应 /
- 三模冗余 /
- 刷新技术 /
- 原位容错 /
- 软错误率
Abstract:
Static random-access memory (SRAM) -based FPGAs are widely used due to their low development cost, short design cycles, and broad adaptability. In applications such as aerospace, military, high-energy nuclear physics, and terrestrial communication systems, these devices face additional requirements for radiation resistance. Therefore, studying soft error protection methods for SRAM-based FPGAs to enhance system reliability has become urgent. This paper categorizes radiation hardening techniques into three levels: hardware-level techniques, system-level techniques, and software-level techniques. It also reviews research in these categories, including hardware hardening, triple modular redundancy (TMR), scrubbing techniques, and algorithm optimization methods. The advantages and disadvantages of each technique are analyzed, and the feasibility and necessity of using in-place fault tolerance as a supplementary technique to further strengthen the TMR + scrubbing design are discussed. Finally, the paper summarizes and provides an outlook on the application of machine learning techniques in this field and proposes a software fault tolerance method based on reinforcement learning. This research aims to offer technical support for the further enhancement of FPGA software radiation resistance methods and provide a reference for researchers in radiation hardening and related fields.
- FPGA /
- single event effect /
- triple modular redundancy /
- scrubbing technique /
- in-place fault tolerance /
- soft error rate

HTML全文

图 1 FPGA平台的系统架构

Figure 1. System architecture of FPGA platform

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图 2 4输入查找表电路结构示意和软错误行为

Figure 2. 4-input look-up table circuit structure and soft error behavior

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图 3 FPGA中不同多路选择器的电路结构

Figure 3. Circuit structure of various multiplexers in FPGA

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图 4 抗辐射加固SRAM单元结构

Figure 4. Structure of radiation-hardened SRAM cells

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图 5 刷新逻辑的不同实现位置

Figure 5. Different implementations of scrubbing

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图 6 基于强化学习的软件容错方法流程

Figure 6. Process of reinforcement learning-based software fault tolerance algorithm

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图 7 配备AI核心的FPGA平台

Figure 7. FPGA platforms with AI cores

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表 1 动态刷新重配置技术分类

Table 1. Dynamic scrubbing reconfiguration techniques classification

分类标准	刷新方法	优势	劣势	实现复杂度	容错效果
按刷新策略	盲刷新	实现难度低，对多粒子翻转事件有效	过多无效刷新提升了单粒子功能中断事件的发生概率	低	中
按刷新策略	基于回读检测的刷新	减少无效刷新次数，对多粒子翻转事件有效	需要额外的比较器电路	中	高
按刷新范围	基于设备的刷新	实现难度低	过多无效刷新提升了单粒子功能中断事件的发生概率	低	中
按刷新范围	基于帧的刷新	降低了单粒子功能中断事件的发生概率	实现复杂度上升，刷新速度减慢	中	高
按刷新时机	按时刷新	实现难度低	容错效果取决于刷新频率，过多无效刷新，功耗较高	低	中
按刷新时机	按需刷新	容错效果好，最小化无效刷新带来的副作用	实现较复杂	较高	较高
按刷新电路位置	外部刷新	鲁棒性高	需外部电路	中	高
按刷新电路位置	内部刷新	实现简单	刷新电路会受到软错误影响	较高	中

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表 2 FPGA在抗辐射环境中采用的片外存储技术

Table 2. Off-chip storage techniques for FPGAs in radiation-resistant environments

存储技术	抗辐射性能		抗辐射应用	描述
存储技术	抗总剂量效应能力	抗单粒子事件能力	抗辐射应用	描述
SRAM	较强	较弱	用于片内配置位存储阵列	采用冗余设计、刷新配置等方法来提高可靠性
反熔丝	免疫	免疫	用于片内配置位存储阵列	仅能单次编程
Flash	较弱	较弱	用于片内配置位存储阵列/ 用于片外存储	密度高，功耗低，单器件容量达512 Mbit
RRAM	强	强	用于片外存储	工作电流低，低功耗下具有高性能
MRAM	强	强	用于片内配置位存储阵列/ 用于片外存储	关键部件免疫辐射效应，兼容CMOS工艺，单器件容量达4 Mbit^[55]
FeRAM	较强	较强	用于片外存储	极强耐用性，工作电流低，单器件容量达2 Mbit^[56]

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表 3 细粒度三模冗余技术分类

Table 3. Fine-grained triple modular redundancy techniques classification

类别	图示说明	占用资源	容错效果
局部三模冗余		较少	较差
分布式三模冗余		平衡	平衡
全局三模冗余		较大	较好
块三模冗余		平衡	平衡

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表 4 不同软件容错方法的比较

Table 4. Comparison of different software fault tolerance algorithms

容错方法	优势	劣势	占用资源	容错效果
在布局布线阶段使用GA和PSO算法	相较于VPR，软错误率降低35%	关键路径增长11%，线长增加14%	中高	中
RoRA算法	相较于三模冗余，容错效果显著提升	相较于三模冗余，布线资源增长8%～38%，平均性能下降22%	高	高
ROSE算法	相较于ABC，查找表减少1%，软错误率降低25%	运行时间长，单独使用容错效果不足	低	中低
IPR方法	相较于ABC，软错误率降低48%	单独使用容错效果不足	低	中
IPF方法	相较于ABC，软错误率降低15%	单独使用容错效果不足	低	中低
R2方法	相较于IPR方法，布线资源减少5%， MTTF提升24%	对电路拓扑结构改变较大	低	中
IPD方法	相较于ABC，软错误率最高下降53%	仅针对查找表进行容错加固，并未加固布线资源	低	中
IPV方法	相较于ABC，软错误率下降61%	基于FPGA学术模型，与商业化FPGA有原理级差异	低	中

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表 5 不同软件容错方法组合的比较

Table 5. Comparison of different combinations of software fault tolerance algorithms

方法组合	对查找表配置位的优化效果/%	对电路级配置位的优化效果/%
IPF+IPD	66.53	19.63
IPF+IPV	17.58	66.29
IPD+IPV	74.34	67.33
IPF+IPD+IPV	66.53	70.24

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