[1] Clein D.CMOS IC layout:concepts,methodologies,and tools[M].Burlington:Newnes Press,1999:63-79[2] Ohring M.Reliability and failure of electronic materials and devices[M].London:Academic Press,1998:339-351[3] Amerasekera E A,Duvvury C.ESD in slicon itegrated crcuits[M].Hoboken:Wiley Press,2002:228-272[4] Ker Ming-Dou,Shu Sheng-Fu.Physical mechanism and device simulation on transient-induced latchup in CMOS ICs under system-level ESD test[J].IEEE Transactions on Electron Devices,2005,52(8):1821-1831[5] Li Tong,Tsai Ching-Han,Rosenbaum E,et al.Modeling,extraction and simulation of CMOS I/O circuits under ESD stress //Proceedings of the International Symposium on Circuits and Systems.Monterey:IEEE,1998(6):389-392[6] Amerasekera A,Ramaswamy S,Chang Mi-Chang,et al.Modeling MOS snapback and parasitic bipolar action for circuit-level ESD and high-current simulations //Proceedings of International Reliability Physics Symposium.Dallas:IEEE,1996:318-326[7] Greason W D.Analysis of human body model for electrostatic discharge(ESD) with multiple charged sources[J].IEEE Transactions on Industry Applications,1994,30(3):589-594[8] Greason W D.Analysis of the charge/discharge processes for the basic ESD models[J].IEEE Transactions on Industry Applications,1993,29(5):887-896[9] Ferreira F K,Moraes F,Reis R.LASCA-interconnect parasitic extraction tool for deep-submicron IC design //Proceedings of the 13th Symposium on Integrated Circuits and Systems Design.Manaus:IEEE,2000:327-332[10] Arora N D,Raol K V,Schumann R,et al.Modeling and extraction of interconnect capacitances for multilayer VLSI circuits[J].IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems,1996,15 (1):58-67[11] Qi Xiaoning,Wang Gaofeng,Yu Zhiping,et al.On-chip inductance modeling and RLC extraction of VLSI interconnects for circuit simulation //Proceedings of the Custom Integrated Circuits Conference.Orlando:IEEE,2000:487-490[12] Yue C P,Wong S S.Physical modeling of spiral inductors on silicon [J].IEEE Transactions on Electron Devices,2000,47(3):560-568[13] JESD22-A114-D Electrostatic discharge (ESD) sensitivity testing human body model (HBM) [S][14] Huo Mingxu,Guo Qing,Gan Yan,et al.A case study of problems in JEDEC HBM ESD test standard [J].IEEE Transactions on Device and Materials Reliability,2009,9(3):361[15] National Semiconductor Corporation:LM741 operational amplifier datasheet .Santa Clara,CA:National Semiconductor Corporation,2000 .
|