Design of multi-FPGAs processor based system for remote sensing image high-speed compression
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摘要: 提出了一种面向海量遥感图像高速压缩应用需求的多现场可编程门阵列(FPGA,Field-Programmable Gate Array),即处理器设计方案,包括针对压缩任务中模块间松耦合和模块内强关联的问题,提出了混合式多FPGA并行处理器结构;给出了包含数据均衡分发和码流规则回收的压缩处理机制,提高了同构FPGA的并行效率,确保压缩处理过程的正确性;给出了支持处理器故障和链路故障的结构容错模型,保证压缩处理过程的可靠性;给出了基于分布式外部存储与高速串行总线的多FPGA通信策略,满足海量遥感图像高速压缩的通信要求.实验结果表明:单片同构FPGA的并行效率达93.5%;应用系统的硬件压缩结果与软件压缩结果一致,计算吞吐率达1.6 Gbit/s以上,并具有高可靠性.Abstract: A design of multi-FPGAs for massive remote sensing image high-speed compression was proposed, which includes a hybrid multi-FPGAs based parallel processor architecture due to light coupling between modules and tight association of a single module; a compression mechanism for balanced data distribution and code stream ordered recycling, which improves parallel efficiency of isomorphic FPGAs and ensures correctness of image compression; a processor failure and link failure supported structure fault-tolerant model, which ensures the reliability of compression; a distributed external storage and high-speed serial bus based communication strategy among multi-FPGAs, which satisfies the communication requirements for massive remote sensing image high-speed compression. Experimental result shows: the parallel efficiency of a single processor achieves 93.5%. In this application system, result of hardware compression is consistent with that of software compression, its throughput reaches 1.6 Gbit/s or more and provides high reliability.
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Key words:
- remote sensing /
- image compression /
- parallel arthitectures /
- fault tolerance
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[1] Hu H.A real-time high resolution image compression system based on ADV212[C]//2009 IEEE International Conference on Image and Signal Processing (CISP).Piscataway,NJ:IEEE Inc,2010:1-4 [2] 葛宝珊,李波.基于多DSP的遥感图像压缩系统[J].计算机工程与设计,2007,28(21):5139-5140,5155 Ge Baoshan,Li Bo.Remote sensing image compression system based on multi-DSP[J].Chinese Journal of Computer Engineering and Design,2007,28(21):5139-5140,5155(in Chinese) [3] Tao Qu,Cong Tang,Zhang Yuyu.The design and implementation of the core algorithm of embedded real-time image compression technology[J].Journal of Key Engineering Materials,2011,480/481:1618-1622 [4] 熊君君,王贞松.星载SAR实时成像处理器的FPGA实现[J].电子学报,2005,33(6):1070-1072 Xiong Junjun,Wang Zhensong.The FPGA design of on board SAR real time imaging processor[J].Chinese Journal of Acta Electronica Sinica,2005,33(6):1070-1072(in Chinese) [5] 文义红.面向遥感图像压缩的视觉量化与位平面编码的算法研究[D].北京:北京航空航天大学计算机学院,2011 Wen Yihong.The study of visual quantization an bit-plane coding algorithms for remote-sensor image[D].Beijing:School of Computer Science and Technology,Beijing University of Aeronautics and Astronautics,2011(in Chinese) [6] Bouriciusw G.Reliability modeling for fault to lerant computers[J].IEEE Tranctions on Computers,1971,C-20:1306-1311 [7] Virtex-5 family overview[DB/OL].San Jose:Xilinx Inc, 2009[2009-02-06].http://www.xilinx.com/support [8] Saripalli V.Exploiting heterogeneity for energy efficiency in chip multiprocessors[J].Emerging and Selected Topics in Circuits and Systems,IEEE Journal on,2011,1(2):109-119 -
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