FPGA-based hardware-efficient architecture for variable block-size motion estimation
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摘要: 针对可变尺寸块运动估计(VBSME,Variable Block-Size Motion Estimation)的硬件结构在现场可编程门阵列(FPGA, Field Programmable Gate Array)上实现时消耗资源多且速度慢的问题,提出了一种面积和速度优化的VBSME硬件结构.其中,绝对差累加和(SAD,Sum of Absolute Differences)的计算采用基于随机存储器(RAM,Random Access Memory)的累加计算方式,比基于寄存器合并的方式节省了面积并增加了速度;通过采用脉动比较链而非总线结构,增强了多个SAD值的比较能力,并能高效地实现对部分差排除算法(PDE,Partial Difference Elimination)的支持.基于Virtex-II型FPGA器件,本结构消耗了2261个slice,时钟频率达到164MHz,在搜索窗口为16×16时可实时处理标清格式的视频.与同类设计相比,设计的面积可减少77%,速度增加218%,FPGA的硬件效率显著提升.Abstract: To improve the hardware efficiency of the FPGA-based(field programmable gate array based)architecture for variable block-size motion estimation, a novel architecture was proposed, which was optimized in both area and speed. This architecture introduced RAM-based SAD(sum of absolute differences) accumulators, which had better performance than register-based combiner in both area and speed. To improve the speed of SADs’ comparison and support partial difference eliminating algorithm, the architecture adopted a systolic comparing chain, which substituted for the bus-based comparator used in former designs. Based on Virtex-II family FPGA from Xilinx Inc., the proposed architecture consumed only 2261 slices, with the clock frequency as high as 164MHz. It means that the architecture could process standard-definition format video with 16×16 search window in real-time. Compared with similar designs, the architecture could save the area by 77% and increase the speed by 218%.
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