二级进位跳跃加法器的优化方块分配

崔晓平; 王成华

二级进位跳跃加法器的优化方块分配

南京航空航天大学信息科学与技术学院, 南京 210016

详细信息

作者简介:
崔晓平(1962-),女,安徽巢湖人,讲师,cuixp126@126.com

中图分类号: TP 342.21
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- 文章访问数: 2719
- HTML全文浏览量: 44
- PDF下载量: 1576
- 被引次数: 0
出版历程
- 收稿日期: 2006-09-19
- 网络出版日期: 2007-04-30

Optimal block distribution in carry-skip adders

College of Information Science and Technology,Nanjing University of Aeronautics and Astronautics, Nanjing 210016, China

摘要

摘要: 提出了一种新的获得二级进位跳跃加法器优化方块分配的算法.根据该算法,在确定最坏路径延时的前提下,首先获得该延时下加法器最大的优化方块尺寸,然后确定任意位二级进位跳跃加法器的优化方块尺寸.优化方块分配的进位跳跃加法器可以缩短关键路径的延时.给出了加法器门级延时、复杂度的分析,分析结果显示,通过优化方块分配,可以以较少的额外门电路获得快速的进位跳跃加法器.该加法器已用PSPICE 仿真工具进行了功能验证和仿真.PSPICE 仿真分析表明,所提出的二级优化方块分配进位跳跃加法器的速度优于等尺寸二级进位跳跃加法器.
- 加法器 /
- 进位跳跃加法器 /
- 门级延时 /
- 优化方块分配
Abstract: A new type of optimal block distribution algorithm of two level carry-skip adder was described to determine optimal block distribution sizes. According to this algorithm, with the given total worst case delay, the maximum optimal block distribution sizes of the adder for that delay can be determined. It is simplified to obtain optimal block distribution of any desired adder sizes. The carry skip adder optimal block sizes can minimize critical path delay. The analysis of gate delay and complexity were provided. Although the two-level carry skip adder with optimal block distribution uses a few extra gates, it provides better speed than the adders with fixed size blocks. The adder has been functionally verified and simulated by using PSPICE. The simulation analysis of time delay reveals that the two-level optimal block distribution carry-skip adder can provide faster speed than the carry-skip adder with fixed size blokes.
- adders /
- carry-skip adder /
- gate delay /
- optimal block distribution

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参考文献(1)

[1] Oklobdzija V G, Zeydel B R, Dao H, et al. Energy-delay estimation technique for high-performance microprocessor VLSI adders Proceedings of the 16th IEEE Symposium on Computer Arithmetic. Los Alamitos, CA, USA :IEEE, 2003:272-279 [2] Nagendra C, Irwin M J, Owens R M. Area-time-power tradeoffs in parallel adders[J]. IEEE Transactions on Circuits and Systems II:Analog and Digital Signal Processing, 1996, 53(10):689-702 [3] 崔晓平,王成华. 基于方块超前进位的快速进位跳跃加法器[J]. 南京航空航天大学学报,2006,38(6):786-790 Cui Xiaoping, Wang Chenghua. Fast carry-skip adder based on block carry-lookahead[J]. Journal of Nanjing University of Aeronautics and Astronautics, 2006, 38(6):786-790(in Chinese) [4] Schulte M J, Chirca K, Glossner J, et al. A low-power carry skip adder with fast saturation Proceedings of the 15th IEEE International Conference on Application-Specific Systems, Architectures and Processors. Los Alamitos, CA, USA :IEEE, 2004:269-279 [5] Burgess N. Accelerated carry-skip adders with low hardware cost Thirty-Fifth Asilomar Conference on Signals, Systems and Computers. Pacific Grove, CA, USA:IEEE, 2001,1(11):852-856 [6] Chan P K, Schlag F, Thomborson C D, et al. Delay optimization of carry-skip adders and block carry-lookahead adders using multidimensional dynamic programming[J]. IEEE Transactions on Computers, 1992, 41(8):154-164 [7] Guyot A, Hochet B, Muller J. A way to build efficient carry-skip adders[J]. IEEE Transactions on Computers, 1987, 36(10):1144-1152 [8] Turrini S. Optimal group distribution in carry-skip adders Proceedings of the 9th Symposium on Computer Arithmetic. Washington, DC, USA :IEEE, 1989:96-103

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